[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc closed 
https://github.com/llvm/llvm-project/pull/101321
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits