Here are some of the particulars:
Our home grown board has two devices on it a CPLD (that
will be
programmed by the time I get it) and an Altera FPGA
EPF10K100A (to be programmed). We will have a .pof file
on the system disk that needs to be written across the PCI
interface, the CPLD program contains a serial interface
emulation to clock the .pof image into the FPGA a byte at
a time. The CPLD will tell the FPGA if it is addressed.
This provides a dynamic aspect to the board.
This is the first time we are trying this, previously
we used an EEprom with the image for the FPGA and no OS.
Thank You.
Eric O. Heinicke [EMAIL PROTECTED]
BAE SYSTEMS Voice:631.262.8644
Fax: 631.262.8657
One Hazeltine Way, MS 1-78
Greenlawn, NY 11740-1606
> -----Original Message-----
> From: Gerald Przybylski [mailto:[EMAIL PROTECTED]]
> Sent: Tuesday, October 10, 2000 12:20
> To: Heinicke, Eric
> Subject: RE: [rtl] Programming a FPGA
>
>
>
> to expand a bit...
> Our mode of operation here, we start by using the ByteBlaster cable
> in conjunction with the Altera design tools to download a
> design to the
> target FPGA.
> The compiler also has a function which takes a .sof file
> (compiler output) and
> massages it into a .jam file.
> Altera has a reference jam player program which believes it
> is writing to the
> equivalent of a parallel port which has byteblaster
> equivalent hardware
> attached, in order to download the configuration into the
> jtag port of the
> FPGA.
>
> If you found an even better way, please share...
>
> Jerry
> Gerald Przybylski
> Phone: (510) 486 7165 FAX: (510) 486 6292
> University of California - Lawrence Berkeley National Laboratory
> http://rust.lbl.gov/~gtp
>
