Re: [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store()

[Richard Henderson]

On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +static bool trans_store(DisasContext *ctx, arg_sb *a, int memop)

gen_store.

>  {
> -    gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
> +    TCGv t0 = tcg_temp_new();
> +    TCGv dat = tcg_temp_new();
> +    gen_get_gpr(t0, a->rs1);
> +    tcg_gen_addi_tl(t0, t0, a->imm);
> +    gen_get_gpr(dat, a->rs2);
> +
> +    if (memop < 0) {
> +        return false;
> +    }

Can't happen.  Otherwise,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>


r~