ACPI 6.4 added Cache ID to the PPTT Cache Type Structure so add id field to CPUCacheInfo.
Add an L2 cache for each of the two clusters in CPUCaches. NOTE: This is hack as it mixes the specifics of the CBQRI example SoC into the the core ACPI AML code. A proper solution would make use of the flexible approach in the "Specifying cache topology on ARM" patch series by Alireza Sanaee. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Drew Fustini <[email protected]> --- include/hw/acpi/aml-build.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 33b303fc833b..2f7551da2b94 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -243,13 +243,15 @@ struct CPUCacheInfo { uint8_t associativity; /* Cache associativity */ uint8_t attributes; /* Cache attributes */ uint16_t line_size; /* Line size in bytes */ + uint32_t id; /* Cache ID - added in ACPI 6.4 */ } CPUCacheInfo; typedef struct CPUCaches { CPUCacheInfo *l1d_cache; CPUCacheInfo *l1i_cache; - CPUCacheInfo *l2_cache; + CPUCacheInfo *l2_cluster1_cache; + CPUCacheInfo *l2_cluster2_cache; CPUCacheInfo *l3_cache; } CPUCaches; -- 2.43.0
