From: Sia Jee Heng <[email protected]> Generate the Processor Properties Topology Table (PPTT) with a cache type 1 structure for RISC-V virtual machine. A 3-layer cache topology is used.
Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Sia Jee Heng <[email protected]> Signed-off-by: Drew Fustini <[email protected]> --- hw/riscv/virt-acpi-build.c | 47 ++++++++++++++++++++++++++++++++++++++++++++++ hw/riscv/virt.c | 1 + 2 files changed, 48 insertions(+) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 210b3f5fff98..5703b0827682 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -40,6 +40,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "system/reset.h" +#include "qemu/units.h" #define ACPI_BUILD_TABLE_SIZE 0x20000 #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index)) @@ -973,6 +974,48 @@ build_srat(GArray *table_data, BIOSLinker *linker, RISCVVirtState *vms) acpi_table_end(linker, &table); } +static void pptt_setup(GArray *table_data, BIOSLinker *linker, MachineState *ms, + const char *oem_id, const char *oem_table_id) +{ + CPUCaches default_cache_info = { + .l1d_cache = &(CPUCacheInfo) { + .type = DATA_CACHE, + .size = 64 * KiB, + .line_size = 64, + .associativity = 4, + .sets = 256, + .attributes = 0x02, + }, + .l1i_cache = &(CPUCacheInfo) { + .type = INSTRUCTION_CACHE, + .size = 64 * KiB, + .line_size = 64, + .associativity = 4, + .sets = 256, + .attributes = 0x04, + }, + .l2_cache = &(CPUCacheInfo) { + .type = UNIFIED_CACHE, + .size = 2048 * KiB, + .line_size = 64, + .associativity = 8, + .sets = 4096, + .attributes = 0x0a, + }, + .l3_cache = &(CPUCacheInfo) { + .type = UNIFIED_CACHE, + .size = 4096 * KiB, + .line_size = 64, + .associativity = 8, + .sets = 8192, + .attributes = 0x0a, + }, + }; + + build_pptt(table_data, linker, ms, oem_id, oem_table_id, + &default_cache_info); +} + static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) { GArray *table_offsets; @@ -1015,6 +1058,10 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) acpi_add_table(table_offsets, tables_blob); build_rqsc(tables_blob, tables->linker, s); + acpi_add_table(table_offsets, tables_blob); + pptt_setup(tables_blob, tables->linker, ms, + s->oem_id, s->oem_table_id); + acpi_add_table(table_offsets, tables_blob); { AcpiMcfgInfo mcfg = { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 99871119be44..491328f7e192 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1929,6 +1929,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data) mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; mc->numa_mem_supported = true; + mc->smp_props.clusters_supported = true; /* platform instead of architectural choice */ mc->cpu_cluster_has_numa_boundary = true; mc->default_ram_id = "riscv_virt_board.ram"; -- 2.43.0
