The GICD_TYPER2 GICv3 distributor register is one that is added for GICv4.1; previously this was architected as a RES0 location. Our TCG GIC doesn't implement GICv4.1, but for KVM the kernel might support it.
This patchset: * makes GICD_TYPER0 reads not trigger a bad-read trace event on the TCG GICv3, for the benefit of GICv4.1-aware guest code * migrates the GICD_TYPER2 register value on a KVM GIC, so that a mismatch between source and destination can be caught by the destination kernel Note that I have only very lightly tested this, on a host which (I believe) doesn't have a GICv4.1. Changes v1->v2: * fix comment missing bracket * fix reset handling so this works on GICv4.1 hosts * move get/put code to be with the other GICD regs * new patch 3 to drop a barely-used debug printf macro thanks -- PMM Peter Maydell (3): hw/intc/arm_gicv3_dist: Implement GICD_TYPER2 as 0 hw/intc/arm_gicv3_kvm: Migrate GICD_TYPER2 hw/intc/arm_gicv3_kvm: Drop DPRINTF macro hw/intc/gicv3_internal.h | 1 + include/hw/intc/arm_gicv3_common.h | 6 +++++ hw/intc/arm_gicv3_common.c | 24 +++++++++++++++++++ hw/intc/arm_gicv3_dist.c | 9 +++++++ hw/intc/arm_gicv3_kvm.c | 38 ++++++++++++++++++------------ 5 files changed, 63 insertions(+), 15 deletions(-) -- 2.43.0
