On Tue, Feb 16, 2016 at 11:38 PM, Or Gerlitz <gerlitz...@gmail.com> wrote:
> On Tue, Feb 16, 2016 at 10:09 PM, Saeed Mahameed <sae...@mellanox.com>
>> @@ -1602,7 +1622,7 @@ static int mlx5e_create_tis(struct mlx5e_priv
> *priv, int tc)
>>
>> memset(in, 0, sizeof(in));
>>
>> - MLX5_SET(tisc, tisc, prio, tc);
>> + MLX5_SET(tisc, tisc, prio, tc << 1);
>
> point bug fix? or we could never hit that prior to the patch as ## TCs
> was always 0?
tc was always 0 before this patch.
>
>> MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
>>
>> return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
>> @@ -1618,7 +1638,7 @@ static int mlx5e_create_tises(struct mlx5e_priv *priv)
>> int err;
>> int tc;
>>
>> - for (tc = 0; tc < priv->params.num_tc; tc++) {
>> + for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
>> err = mlx5e_create_tis(priv, tc);
>
> various places in the patch use priv->params.num_tc, wasn't sure if
> it's correct to hard code things here, and if it does, why not hard
> code everywhere
TISs and TIRs unlike SQs and RQs are created once on driver load, so
we create the MAX supported TISs (TIS per prio) and when you create
the rings/channels (SQs) we create them according to the dynamic
"priv->params.num_tc" and then we assign the pre allocated TIS to the
SQ according to SQ TC/Prio configuration.
