================
@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma
vsetvli a2, a0, e32, mf2, ta, ma
# CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible
with all RVV implementations{{$}}
# CHECK-ENCODING: [0x57,0x76,0x75,0x0d]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for
Application Processors), 'Zve32x' (Vector Extensions for Embedded
Processors){{$}}
# CHECK-UNKNOWN: 0d757657 <unknown>
vsetvli a2, a0, e32, mf4, ta, ma
# CHECK-INST: vsetvli a2, a0, e32, mf4, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 8 may not be compatible with
all RVV implementations{{$}}
----------------
wangpc-pp wrote:
I suppose we should.
One example I just met days ago:
```c
int main() {
asm("vsetivli zero, 1, e32, mf4, ta, ma\n"
"csrr a0, vtype\n"
"csrr a1, vlenb\n"
"vmv.s.x v24, a6");
return 0;
}
```
For MF4, the must supported SEWs are [8, 16], while the SEW is 32 here.
For C908 core on K230 board, this code will crash with an `Illegal Instruction`
error, but not on `qemu`.
The `vlen` of C908 is 128 bits, theoretically, for MF4, we can store one
element in a vector register. But the implementation sets `vill` for this
configuration (this is not against the RVV spec, though).
So I think we should warn as it can be incompatible.
https://github.com/llvm/llvm-project/pull/94313
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