llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-mc Author: Pengcheng Wang (wangpc-pp) <details> <summary>Changes</summary> According to RVV spec: > In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, > where SEWMIN is the narrowest supported SEW value and ELEN is > the widest supported SEW value. > > For a given supported fractional LMUL setting, implementations > must support SEW settings between SEWMIN and LMUL * ELEN, inclusive. We print a warning if these requirements are not met. --- Full diff: https://github.com/llvm/llvm-project/pull/94313.diff 2 Files Affected: - (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+22) - (modified) llvm/test/MC/RISCV/rvv/vsetvl.s (+5) ``````````diff diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index d92998ced91ef..4295e98ff2fa8 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -2155,6 +2155,17 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State, break; if (!RISCVVType::isValidLMUL(Lmul, Fractional)) break; + + if (Fractional) { + unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 : 32; + unsigned MinLMUL = ELEN / 8; + if (Lmul > MinLMUL) + Warning( + Tok.getLoc(), + Twine("LMUL < mf") + Twine(MinLMUL) + + Twine(" may not be compatible with all RVV implementations")); + } + State = VTypeState_TailPolicy; return false; } @@ -2194,6 +2205,7 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) { bool MaskAgnostic = false; VTypeState State = VTypeState_SEW; + SMLoc SEWLoc = S; if (parseVTypeToken(getTok(), State, Sew, Lmul, Fractional, TailAgnostic, MaskAgnostic)) @@ -2211,6 +2223,16 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) { if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) { RISCVII::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional); + if (Fractional) { + unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 : 32; + unsigned MaxSEW = ELEN / Lmul; + // If MaxSEW < 8, we should have printed warning about incompatible LMUL. + if (MaxSEW >= 8 && Sew > MaxSEW) + Warning( + SEWLoc, + Twine("SEW > ") + Twine(MaxSEW) + + Twine(" may not be compatible with all RVV implementations")); + } unsigned VTypeI = RISCVVType::encodeVTYPE(VLMUL, Sew, TailAgnostic, MaskAgnostic); diff --git a/llvm/test/MC/RISCV/rvv/vsetvl.s b/llvm/test/MC/RISCV/rvv/vsetvl.s index c9197d8917a47..d61e8f48445d4 100644 --- a/llvm/test/MC/RISCV/rvv/vsetvl.s +++ b/llvm/test/MC/RISCV/rvv/vsetvl.s @@ -1,5 +1,7 @@ # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+v %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-WARNING # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v %s \ @@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma vsetvli a2, a0, e32, mf2, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma +# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible with all RVV implementations{{$}} # CHECK-ENCODING: [0x57,0x76,0x75,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 0d757657 <unknown> vsetvli a2, a0, e32, mf4, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf4, ta, ma +# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 8 may not be compatible with all RVV implementations{{$}} # CHECK-ENCODING: [0x57,0x76,0x65,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 0d657657 <unknown> vsetvli a2, a0, e32, mf8, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf8, ta, ma +# CHECK-WARNING: :[[#@LINE-2]]:22: warning: LMUL < mf4 may not be compatible with all RVV implementations{{$}} # CHECK-ENCODING: [0x57,0x76,0x55,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 0d557657 <unknown> `````````` </details> https://github.com/llvm/llvm-project/pull/94313 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
