ted added a comment. In D155107#4534020 <https://reviews.llvm.org/D155107#4534020>, @clayborg wrote:
> So Ted, can you verify that nothing is missing in RISCV since this is already > the way it works for x86/x86_64 and arm32/arm64? I am thinking like Jason is > where I wonder if something isn't just hooked up right for RISCV somehow. Or > if you can verify that nothing changes for x86/x86_64 or arm32/arm64 if this > setting is enabled and there are no symbolication regressions in the comments > if this does get enabled for the architectures where it is working as > expected... I can verify that this change doesn't break RISC-V disassembly. I can't verify that nothing is missing. In fact, our current disassembler doesn't recognize most change-of-flow instructions, because the RISC-V disassembler doesn't populate the MCInstrDesc for them correctly. There's a diff D156086 <https://reviews.llvm.org/D156086> to handle that, though (use MCInstrAnalysis if it's there). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155107/new/ https://reviews.llvm.org/D155107 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
