ted added a comment.
In D155107#4511967 <https://reviews.llvm.org/D155107#4511967>, @clayborg wrote:
> Looks like other disassemblers already show full addresses for the branches
> and calls (at least arm64 does from my output above), so not sure why RISCV
> would require this setting, but x86_64 and arm64 wouldn't because it is
> already working that way??
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp has this code,
specifically using PrintBranchImmAsAddress to gate this behavior:
void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNo);
if (!MO.isImm())
return printOperand(MI, OpNo, STI, O);
if (PrintBranchImmAsAddress) {
uint64_t Target = Address + MO.getImm();
if (!STI.hasFeature(RISCV::Feature64Bit))
Target &= 0xffffffff;
O << formatHex(Target);
} else {
O << MO.getImm();
}
}
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D155107/new/
https://reviews.llvm.org/D155107
_______________________________________________
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
