jasonmolenda accepted this revision. jasonmolenda added a comment. This revision is now accepted and ready to land.
Looking at Ted's earlier riscv disassembly with this enabled, it is more readable, I'm surprised these instructions don't print this way by default like they are for other targets. My two cents, I'm fine with landing this, and if we find that another target's disassembly is poorer, we can look into that more closely. I had a quick attempt at aarch64 that would disassemble differently but didn't succeed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155107/new/ https://reviews.llvm.org/D155107 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
