labath added a comment. The idea seems nice, however I am wondering, if it is not going a bit too far. In not sure of the exact situation on arm64, but in general, there are registers which only accept some bit patterns. What exactly does ptrace do in this situation? Postponing the write until we resume/detach means we lose the opportunity to report any errors that would result from the ptrace call.
What's the exact case you're optimising for? Would it be enough to just cache the reads, but then as soon as we write something, we immediately call ptrace to ensure that the value was written successfully? It sounds like this could be enough as the majority of the operations should be reads... ================ Comment at: source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h:153-154 + bool m_gpr_is_valid; + bool m_fpu_is_valid; + ---------------- Please move these next to the members they are guarding. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69371/new/ https://reviews.llvm.org/D69371 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
