On Fri, Jul 03, 2026 at 05:31:13AM -0700, Ananthu C V wrote: > From: Sibi Sankar <[email protected]> > > The SoC Control Processor (SoCCP) is a small RISC-V MCU that controls > USB Type-C, battery charging and various other functions on Qualcomm SoCs.
This sounds like a good description of the SoCCP, excellent start of the commit message. > It provides a solution for control-plane processing, reducing per-subsystem > microcontroller reinvention. But, not only did the first sentence come to a full stop, this sentence is also trying to describe the purpose of the SoCCP - but the scope doesn't seem to overlap, so this seems to hint that there's more to it than what was first established... Please fix. > Add PAS loader for SoCCP on Glymur DT. And once you have established the problem description across multiple sentences, break the paragraph to give the reader some breathing/thinking room, before documenting the "user-visible change" of the patch. Regards, Bjorn > > Signed-off-by: Sibi Sankar <[email protected]> > Co-developed-by: Ananthu C V <[email protected]> > Signed-off-by: Ananthu C V <[email protected]> > --- > arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 +++++ > arch/arm64/boot/dts/qcom/glymur.dtsi | 44 > ++++++++++++++++++++++++++++++++ > 2 files changed, 51 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi > b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi > index e784b538f42e..328eb513140f 100644 > --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi > +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi > @@ -585,6 +585,13 @@ &remoteproc_cdsp { > status = "okay"; > }; > > +&remoteproc_soccp { > + firmware-name = "qcom/glymur/soccp.mbn", > + "qcom/glymur/soccp_dtb.mbn"; > + > + status = "okay"; > +}; > + > &tlmm { > gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ > <10 2>, /* OOB UART */ > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi > b/arch/arm64/boot/dts/qcom/glymur.dtsi > index 5f44f68efde2..bc259dfbaf0e 100644 > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi > @@ -2297,6 +2297,50 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, > }; > }; > > + remoteproc_soccp: remoteproc@d00000 { > + compatible = "qcom,glymur-soccp-pas"; > + reg = <0x0 0x00d00000 0x0 0x200000>; > + > + interrupts-extended = <&intc GIC_SPI 167 > IRQ_TYPE_EDGE_RISING>, > + <&soccp_smp2p_in 0 > IRQ_TYPE_EDGE_RISING>, > + <&soccp_smp2p_in 1 > IRQ_TYPE_EDGE_RISING>, > + <&soccp_smp2p_in 2 > IRQ_TYPE_EDGE_RISING>, > + <&soccp_smp2p_in 3 > IRQ_TYPE_EDGE_RISING>, > + <&soccp_smp2p_in 9 > IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "wdog", > + "fatal", > + "ready", > + "handover", > + "stop-ack", > + "pong"; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "xo"; > + > + power-domains = <&rpmhpd RPMHPD_CX>, > + <&rpmhpd RPMHPD_MX>; > + power-domain-names = "cx", > + "mx"; > + > + memory-region = <&soccp_mem>, > + <&soccpdtb_mem>; > + > + qcom,smem-states = <&soccp_smp2p_out 0>, > + <&soccp_smp2p_out 8>; > + qcom,smem-state-names = "stop", > + "ping"; > + > + glink-edge { > + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP > + > IPCC_MPROC_SIGNAL_GLINK_QMP > + > IRQ_TYPE_EDGE_RISING>; > + mboxes = <&ipcc IPCC_MPROC_SOCCP > + IPCC_MPROC_SIGNAL_GLINK_QMP>; > + qcom,remote-pid = <19>; > + label = "soccp"; > + }; > + }; > + > usb_hs_phy: phy@fa0000 { > compatible = "qcom,glymur-m31-eusb2-phy", > "qcom,sm8750-m31-eusb2-phy"; > > -- > 2.43.0 >
