On 09/11/2025 10:39, David Heidelberg via B4 Relay wrote:
From: David Heidelberg <[email protected]>
So far, only D-PHY mode was supported, which uses even bits when enabling
or masking lanes. For C-PHY configuration, the hardware instead requires
using the odd bits.
Signed-off-by: David Heidelberg <[email protected]>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 25 ++++++++++++++++------
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index f28c32d1a4ec5..348b8cd18327e 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -1054,10 +1054,17 @@ static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg
*lane_cfg)
u8 lane_mask;
int i;
- lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
+ if (lane_cfg->cphy) {
+ lane_mask = 0;
- for (i = 0; i < lane_cfg->num_data; i++)
- lane_mask |= 1 << lane_cfg->data[i].pos;
+ for (i = 0; i < lane_cfg->num_data; i++)
+ lane_mask |= (1 << lane_cfg->data[i].pos) + 1;
+ } else {
+ lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
+
+ for (i = 0; i < lane_cfg->num_data; i++)
+ lane_mask |= 1 << lane_cfg->data[i].pos;
+ }
return lane_mask;
}
@@ -1096,10 +1103,14 @@ static void csiphy_lanes_enable(struct csiphy_device
*csiphy,
settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
- val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
- for (i = 0; i < c->num_data; i++)
- val |= BIT(c->data[i].pos * 2);
-
+ if (c->cphy) {
Imagine val is initialized here:
val = 0;
is already fixed in next version.
+ for (i = 0; i < c->num_data; i++)
+ val |= BIT((c->data[i].pos * 2) + 1);
+ } else {
+ val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
+ for (i = 0; i < c->num_data; i++)
+ val |= BIT(c->data[i].pos * 2);
+ }
writel_relaxed(val, csiphy->base +
CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5));
--
David Heidelberg
