On 11/5/2025 1:01 AM, Konrad Dybcio wrote:
> From: Konrad Dybcio <[email protected]>
>
> To make sure that power rail is voted for, wire it up to its consumers.
>
> Fixes: 9bd07f2c558f ("arm64: dts: qcom: sc8280xp: Add in CAMCC for sc8280xp")
> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 22 ++++++++++++++++------
> 1 file changed, 16 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 5334adebf278..643a61cc91b4 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -4586,8 +4586,10 @@ camcc: clock-controller@ad00000 {
> <&rpmhcc RPMH_CXO_CLK>,
> <&rpmhcc RPMH_CXO_CLK_A>,
> <&sleep_clk>;
> - power-domains = <&rpmhpd SC8280XP_MMCX>;
> - required-opps = <&rpmhpd_opp_low_svs>;
> + power-domains = <&rpmhpd SC8280XP_MMCX>,
> + <&rpmhpd SC8280XP_MXC>;
I see that none of the CAMCC PLLs/clocks are on MXC rail on SC8280XP target.
So, MXC support is not required for CAMCC.
Thanks,
Imran
> + required-opps = <&rpmhpd_opp_low_svs>,
> + <&rpmhpd_opp_low_svs>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> #power-domain-cells = <1>;
> @@ -5788,8 +5790,12 @@ remoteproc_nsp0: remoteproc@1b300000 {
> clocks = <&rpmhcc RPMH_CXO_CLK>;
> clock-names = "xo";
>
> - power-domains = <&rpmhpd SC8280XP_NSP>;
> - power-domain-names = "nsp";
> + power-domains = <&rpmhpd SC8280XP_NSP>,
> + <&rpmhpd SC8280XP_CX>,
> + <&rpmhpd SC8280XP_MXC>;
> + power-domain-names = "nsp",
> + "cx",
> + "mxc";
>
> memory-region = <&pil_nsp0_mem>;
>
> @@ -5919,8 +5925,12 @@ remoteproc_nsp1: remoteproc@21300000 {
> clocks = <&rpmhcc RPMH_CXO_CLK>;
> clock-names = "xo";
>
> - power-domains = <&rpmhpd SC8280XP_NSP>;
> - power-domain-names = "nsp";
> + power-domains = <&rpmhpd SC8280XP_NSP>,
> + <&rpmhpd SC8280XP_CX>,
> + <&rpmhpd SC8280XP_MXC>;
> + power-domain-names = "nsp",
> + "cx",
> + "mxc";
>
> memory-region = <&pil_nsp1_mem>;
>
>
