On 25-10-21 20:08:55, Luca Weiss wrote:
> The 'Agera' PLLs (with clk_agera_pll_configure) do not take some of the
> parameters that are provided in the vendor driver. Instead the upstream
> configuration should provide the final user_ctl value that is written to
> the USER_CTL register.
>
> Fix the config so that the PLL is configured correctly.
>
> Fixes: 9f0532da4226 ("clk: qcom: Add Camera Clock Controller driver for
> SM7150")
> Suggested-by: Taniya Das <[email protected]>
> Signed-off-by: Luca Weiss <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
