> Subject: [PATCH v2 06/24] drm/i915/lt_phy: Add xe3plpd .compute_dplls hook > > Add compute dpll hook for xe3plpd platform and bring PLL state calculation to > support PLL framework. > > Signed-off-by: Mika Kahola <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dpll.c | 2 +- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65 +++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_lt_phy.c | 17 +++-- > drivers/gpu/drm/i915/display/intel_lt_phy.h | 3 +- > 4 files changed, 78 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c > b/drivers/gpu/drm/i915/display/intel_dpll.c > index 8433e3ff0319..147baa777856 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c > @@ -1222,7 +1222,7 @@ static int xe3plpd_crtc_compute_clock(struct > intel_atomic_state *state, > struct intel_display *display = to_intel_display(encoder); > int ret; > > - ret = intel_lt_phy_pll_calc_state(crtc_state, encoder); > + ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, > +&crtc_state->dpll_hw_state); > if (ret) > return ret; > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index 4185c8e136da..58c24e2164ca 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -4585,9 +4585,74 @@ static const struct dpll_info xe3plpd_plls[] = { > {} > }; > > +static int xe3plpd_compute_non_tc_phy_dpll(struct intel_atomic_state > *state, > + struct intel_crtc *crtc, > + struct intel_encoder *encoder) > +{ > + struct intel_display *display = to_intel_display(encoder); > + struct intel_crtc_state *crtc_state = > + intel_atomic_get_new_crtc_state(state, crtc); > + struct icl_port_dpll *port_dpll = > + &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; > + int ret; > + > + ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll- > >hw_state); > + if (ret) > + return ret; > + > + /* this is mainly for the fastset check */ > + icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); > + > + crtc_state->port_clock = intel_lt_phy_calc_port_clock(display, > +&port_dpll->hw_state.ltpll); > + > + return 0; > +} > + > +static int xe3plpd_compute_tc_phy_dplls(struct intel_atomic_state *state, > + struct intel_crtc *crtc, > + struct intel_encoder *encoder) > +{ > + struct intel_display *display = to_intel_display(encoder); > + struct intel_crtc_state *crtc_state = > + intel_atomic_get_new_crtc_state(state, crtc); > + const struct intel_crtc_state *old_crtc_state = > + intel_atomic_get_old_crtc_state(state, crtc); > + struct icl_port_dpll *port_dpll; > + int ret; > + > + /* TODO: Add state calculation for TBT PLL */ > + > + port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; > + ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll- > >hw_state); > + if (ret) > + return ret; > + > + /* this is mainly for the fastset check */ > + if (old_crtc_state->intel_dpll && > + old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL) > + icl_set_active_port_dpll(crtc_state, > ICL_PORT_DPLL_DEFAULT); > + else > + icl_set_active_port_dpll(crtc_state, > ICL_PORT_DPLL_MG_PHY); > + > + crtc_state->port_clock = intel_lt_phy_calc_port_clock(display, > +&port_dpll->hw_state.ltpll); > + > + return 0; > +} > + > +static int xe3plpd_compute_dplls(struct intel_atomic_state *state, > + struct intel_crtc *crtc, > + struct intel_encoder *encoder) > +{ > + if (intel_encoder_is_tc(encoder)) > + return xe3plpd_compute_tc_phy_dplls(state, crtc, encoder); > + else > + return xe3plpd_compute_non_tc_phy_dpll(state, crtc, > encoder); } > + > __maybe_unused > static const struct intel_dpll_mgr xe3plpd_pll_mgr = { > .dpll_info = xe3plpd_plls, > + .compute_dplls = xe3plpd_compute_dplls, > }; > > /** > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c > b/drivers/gpu/drm/i915/display/intel_lt_phy.c > index 07eab4d7bcff..ca31b3c1440c 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c > @@ -1727,12 +1727,15 @@ intel_lt_phy_calc_port_clock(struct intel_display > *display, > > int > intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state, > - struct intel_encoder *encoder) > + struct intel_encoder *encoder, > + struct intel_dpll_hw_state *hw_state)
I would rather this be named dpll_state But I do see everywhere else it is name hw_state so I am okay either way LGTM Reviewed-by: Suraj Kandpal <[email protected]> > { > struct intel_display *display = to_intel_display(crtc_state); > const struct intel_lt_phy_pll_params *tables; > int i; > > + memset(hw_state, 0, sizeof(*hw_state)); > + > tables = intel_lt_phy_pll_tables_get(crtc_state, encoder); > if (!tables) > return -EINVAL; > @@ -1742,21 +1745,21 @@ intel_lt_phy_pll_calc_state(struct > intel_crtc_state *crtc_state, > > drm_WARN_ON(display->drm, > !intel_dpll_clock_matches(clock, tables[i].clock_rate)); > if (intel_dpll_clock_matches(crtc_state->port_clock, clock)) { > - crtc_state->dpll_hw_state.ltpll = *tables[i].state; > + hw_state->ltpll = *tables[i].state; > if (intel_crtc_has_dp_encoder(crtc_state)) { > if (intel_crtc_has_type(crtc_state, > INTEL_OUTPUT_EDP)) > - crtc_state- > >dpll_hw_state.ltpll.config[2] = 1; > + hw_state->ltpll.config[2] = 1; > } > - crtc_state->dpll_hw_state.ltpll.ssc_enabled = > + hw_state->ltpll.ssc_enabled = > intel_lt_phy_pll_is_ssc_enabled(crtc_state, > encoder); > - crtc_state->dpll_hw_state.ltpll.lane_count = > crtc_state->lane_count; > + hw_state->ltpll.lane_count = crtc_state->lane_count; > return 0; > } > } > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { > - crtc_state->dpll_hw_state.ltpll.lane_count = crtc_state- > >lane_count; > - return intel_lt_phy_calculate_hdmi_state(&crtc_state- > >dpll_hw_state.ltpll, > + hw_state->ltpll.lane_count = crtc_state->lane_count; > + return intel_lt_phy_calculate_hdmi_state(&hw_state->ltpll, > crtc_state- > >port_clock); > } > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h > b/drivers/gpu/drm/i915/display/intel_lt_phy.h > index db905668f86d..61ec0e5d8888 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h > @@ -20,7 +20,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder > *encoder, void intel_lt_phy_pll_disable(struct intel_encoder *encoder); int > intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state, > - struct intel_encoder *encoder); > + struct intel_encoder *encoder, > + struct intel_dpll_hw_state *hw_state); > int intel_lt_phy_calc_port_clock(struct intel_display *display, > const struct intel_lt_phy_pll_state *lt_state); > void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder, > -- > 2.43.0
