> Subject: [PATCH v2 05/24] drm/i915/lt_phy: Add lane_count to PLL state > > Cache lane count as part of PLL state. > > Signed-off-by: Mika Kahola <[email protected]>
LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + > drivers/gpu/drm/i915/display/intel_lt_phy.c | 9 +++++---- > 2 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > index 4cc14ce5eebe..d408ccf6f902 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > @@ -278,6 +278,7 @@ struct intel_lt_phy_pll_state { > u8 config[3]; > bool ssc_enabled; > bool tbt_mode; > + int lane_count; > }; > > struct intel_dpll_hw_state { > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c > b/drivers/gpu/drm/i915/display/intel_lt_phy.c > index ebdcab58df4a..07eab4d7bcff 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c > @@ -1749,11 +1749,13 @@ intel_lt_phy_pll_calc_state(struct > intel_crtc_state *crtc_state, > } > crtc_state->dpll_hw_state.ltpll.ssc_enabled = > intel_lt_phy_pll_is_ssc_enabled(crtc_state, > encoder); > + crtc_state->dpll_hw_state.ltpll.lane_count = > crtc_state->lane_count; > return 0; > } > } > > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { > + crtc_state->dpll_hw_state.ltpll.lane_count = crtc_state- > >lane_count; > return intel_lt_phy_calculate_hdmi_state(&crtc_state- > >dpll_hw_state.ltpll, > crtc_state- > >port_clock); > } > @@ -1793,11 +1795,11 @@ intel_lt_phy_program_pll(struct intel_encoder > *encoder, > > static void > intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder, > - const struct intel_lt_phy_pll_state *ltpll, > - u8 lane_count) > + const struct intel_lt_phy_pll_state *ltpll) > { > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > bool lane_reversal = dig_port->lane_reversal; > + u8 lane_count = ltpll->lane_count; > bool is_dp_alt = > intel_tc_port_in_dp_alt_mode(dig_port); > enum intel_tc_pin_assignment tc_pin = > @@ -2006,8 +2008,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder > *encoder, > intel_lt_phy_powerdown_change_sequence(encoder, > owned_lane_mask, > XELPDP_P0_STATE_ACTIVE); > > - intel_lt_phy_enable_disable_tx(encoder, &crtc_state- > >dpll_hw_state.ltpll, > - crtc_state->lane_count); > + intel_lt_phy_enable_disable_tx(encoder, > +&crtc_state->dpll_hw_state.ltpll); > intel_lt_phy_transaction_end(encoder, wakeref); } > > -- > 2.43.0
