> Subject: [PATCH v2 02/24] drm/i915/lt_phy: Add check if PLL is enabled
>
> Add check for PLL enabling and return early if PLL is not enabled.
>
> v2: Use PCLK PLL request to check if PLL is enabled (Suraj)
>
> Signed-off-by: Mika Kahola <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 24 +++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index f768804122c1..8fe61cfdb706 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -2176,6 +2176,27 @@ intel_lt_phy_pll_compare_hw_state(const struct
> intel_lt_phy_pll_state *a,
> return false;
> }
>
> +static u32 intel_lt_phy_get_pclk_pll_ack(u8 lane_mask) {
> + u32 val = 0;
> + int lane = 0;
> +
> + for_each_lt_phy_lane_in_mask(lane_mask, lane)
> + val |= XELPDP_LANE_PCLK_PLL_ACK(lane);
> +
I think you forgot to implement the changes here they patch looks identical to
previous one.
Maybe I wasn't able to get my point across properly.
Leaving the same comment again
unlike CX0 PHY where we the step is
Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK**> to "1" to
enable PLL.
That is not the case for LT PHY there we request and wait for ACK on Lane 0
Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. This will assert the MacCLK
Request.
Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. This is the MacCLKAck assertion.
Expected MACCLK_TURNON_LATENCY is 100 us.
So all we need to do is check PCLK PLL ACK on LN0
Regards,
Suraj Kandpal
> + return val;
> +}
> +
> +static bool intel_lt_phy_pll_is_enabled(struct intel_encoder *encoder)
> +{
> + struct intel_display *display = to_intel_display(encoder);
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + u8 lane = dig_port->lane_reversal ? INTEL_LT_PHY_LANE1 :
> +INTEL_LT_PHY_LANE0;
> +
> + return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port)) &
> + intel_lt_phy_get_pclk_pll_ack(lane);
> +}
> +
> void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
> const struct intel_crtc_state
> *crtc_state,
> struct intel_lt_phy_pll_state *pll_state)
> @@ -2185,6 +2206,9 @@ void intel_lt_phy_pll_readout_hw_state(struct
> intel_encoder *encoder,
> struct ref_tracker *wakeref;
> int i, j, k;
>
> + if (!intel_lt_phy_pll_is_enabled(encoder))
> + return;
> +
> pll_state->tbt_mode =
> intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
> if (pll_state->tbt_mode)
> return;
> --
> 2.43.0
