On Mon, 2025-10-13 at 12:50 +0300, Mika Kahola wrote:
> From: Imre Deak <[email protected]>
> 
> Clock value is missing from C10 hw readout stage. Let's fix this.
> 
> Signed-off-by: Imre Deak <[email protected]>
> Signed-off-by: Mika Kahola <[email protected]>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c       | 5 +++++
>  drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c | 2 ++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f8c1338f9053..a74c1be225ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2103,6 +2103,9 @@ static int intel_c10pll_calc_state(struct 
> intel_crtc_state *crtc_state,
>       return 0;
>  }
>  
> +static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> +                                     const struct intel_c10pll_state 
> *pll_state);
> +
>  static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
>                                         struct intel_c10pll_state *pll_state)
>  {
> @@ -2127,6 +2130,8 @@ static void intel_c10pll_readout_hw_state(struct 
> intel_encoder *encoder,
>       pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0));
>  
>       intel_cx0_phy_transaction_end(encoder, wakeref);
> +
> +     pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
>  }
>  
>  static void intel_c10_pll_program(struct intel_display *display,
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c 
> b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> index 7fe6b4a18213..a201edceee10 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
> @@ -332,6 +332,8 @@ void intel_snps_hdmi_pll_compute_c10pll(struct 
> intel_c10pll_state *pll_state, u6
>                             c10_curve_1, c10_curve_2, prescaler_divider,
>                             &pll_params);
>  
> +     pll_state->clock = pixel_clock;
> +
>       pll_state->tx = 0x10;
>       pll_state->cmn = 0x1;
>       pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, 
> pll_params.mpll_div5_en) |

Reviewed-by: Luca Coelho <[email protected]>

--
Cheers,
Luca.

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