On Mon, 2025-10-13 at 12:50 +0300, Mika Kahola wrote: > From: Imre Deak <[email protected]> > > Rename the PHY_C20_CUSTOM_SERDES / PHY_C20_CUSTOM_SERDES_MASK register > field names to PHY_C20_DP_RATE / PHY_C20_DP_RATE_MASK, and move the > definitions under the actual register containing the fields. > > Signed-off-by: Imre Deak <[email protected]> > Signed-off-by: Mika Kahola <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 +++--- > drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++-- > 2 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index a2d2cecf7121..0d83145eff41 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2700,12 +2700,12 @@ static void intel_c20_pll_program(struct > intel_display *display, > /* 5. For DP or 6. For HDMI */ > if (is_dp) { > intel_cx0_rmw(encoder, owned_lane_mask, > PHY_C20_VDR_CUSTOM_SERDES_RATE, > - BIT(6) | PHY_C20_CUSTOM_SERDES_MASK, > - BIT(6) | > PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(port_clock)), > + BIT(6) | PHY_C20_DP_RATE_MASK, > + BIT(6) | > PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)), > MB_WRITE_COMMITTED); > } else { > intel_cx0_rmw(encoder, owned_lane_mask, > PHY_C20_VDR_CUSTOM_SERDES_RATE, > - BIT(7) | PHY_C20_CUSTOM_SERDES_MASK, > + BIT(7) | PHY_C20_DP_RATE_MASK, > is_hdmi_frl(port_clock) ? BIT(7) : 0, > MB_WRITE_COMMITTED); > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > index 77eae1d845f7..25ab8808e548 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > @@ -298,10 +298,10 @@ > #define PHY_C20_RD_DATA_L 0xC08 > #define PHY_C20_RD_DATA_H 0xC09 > #define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00 > +#define PHY_C20_DP_RATE_MASK REG_GENMASK8(4, 1) > +#define PHY_C20_DP_RATE(val) > REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val) > #define PHY_C20_VDR_HDMI_RATE 0xD01 > #define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0) > -#define PHY_C20_CUSTOM_SERDES_MASK REG_GENMASK8(4, 1) > -#define PHY_C20_CUSTOM_SERDES(val) > REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val) > #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02 > #define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0) > #define PHY_C20_CUSTOM_WIDTH(val) > REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
Reviewed-by: Luca Coelho <[email protected]> -- Cheers, Luca.
