On Mon, 2025-10-13 at 12:50 +0300, Mika Kahola wrote: > From: Imre Deak <[email protected]> > > Define PHY_C20_IS_HDMI_FRL, so it can be used instead of the plain bit number. > > Signed-off-by: Imre Deak <[email protected]> > Signed-off-by: Mika Kahola <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 ++-- > drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 1 + > 2 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index a7aee098e7b9..9be7e155a584 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2706,8 +2706,8 @@ static void intel_c20_pll_program(struct intel_display > *display, > MB_WRITE_COMMITTED); > } else { > intel_cx0_rmw(encoder, owned_lane_mask, > PHY_C20_VDR_CUSTOM_SERDES_RATE, > - BIT(7) | PHY_C20_DP_RATE_MASK, > - is_hdmi_frl(port_clock) ? BIT(7) : 0, > + PHY_C20_IS_HDMI_FRL | PHY_C20_DP_RATE_MASK, > + is_hdmi_frl(port_clock) ? PHY_C20_IS_HDMI_FRL : 0, > MB_WRITE_COMMITTED); > > intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, > PHY_C20_VDR_HDMI_RATE, > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > index 5bd1e02b5313..0743a3e2d15f 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > @@ -298,6 +298,7 @@ > #define PHY_C20_RD_DATA_L 0xC08 > #define PHY_C20_RD_DATA_H 0xC09 > #define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00 > +#define PHY_C20_IS_HDMI_FRL REG_BIT8(7) > #define PHY_C20_IS_DP REG_BIT8(6) > #define PHY_C20_DP_RATE_MASK REG_GENMASK8(4, 1) > #define PHY_C20_DP_RATE(val) > REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
Reviewed-by: Luca Coelho <[email protected]> -- Cheers, Luca.
