Add enable/disable frame counters for DC Balance odd and even frame count calculation.
--v2: Update commit message --v3: - Driver should not control adjustment enable bit, as that is already being controlled by firmware. Release bit from driver computation. - Commit message update. --v4: - Configure PIPEDMC_EVT_CTL enable/disable call. --v5: - Add Adaptive sync counter enable. Signed-off-by: Mitul Golani <[email protected]> --- drivers/gpu/drm/i915/display/intel_vrr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 5eb4a7e97291..d5359a96054b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -686,6 +686,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) ctl |= VRR_CTL_CMRR_ENABLE; if (crtc_state->vrr.dc_balance.enable) { + intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), + ADAPTIVE_SYNC_COUNTER_EN); intel_dmc_configure_dc_balance_ctl_regs(display, pipe, true); intel_pipedmc_dcb_enable(NULL, crtc); } @@ -707,6 +709,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) if (old_crtc_state->vrr.dc_balance.enable) { intel_pipedmc_dcb_disable(NULL, crtc); intel_dmc_configure_dc_balance_ctl_regs(display, pipe, false); + intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0); } ctl = trans_vrr_ctl(old_crtc_state); -- 2.48.1
