Configure PIPEDMC_EVT_CTL_3 register with required event flags. --v2: - Initialize with redundant flags. (Ankit)
Signed-off-by: Mitul Golani <[email protected]> --- drivers/gpu/drm/i915/display/intel_dmc.c | 17 +++++++++++++++++ drivers/gpu/drm/i915/display/intel_dmc.h | 2 ++ drivers/gpu/drm/i915/display/intel_vrr.c | 8 ++++++-- 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 1726c0ab18c2..3b81a7b48035 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -810,6 +810,23 @@ void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0); } +void intel_dmc_configure_dc_balance_ctl_regs(struct intel_display *display, + enum pipe pipe, bool enable) +{ + u32 val = REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, + DMC_EVT_CTL_TYPE_EDGE_0_1); + + if (enable) + val |= DMC_EVT_CTL_ENABLE | DMC_EVT_CTL_RECURRING | + REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, + PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER); + else + val |= REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, + DMC_EVENT_FALSE); + + intel_de_write(display, PIPEDMC_EVT_CTL_3(pipe), val); +} + /** * intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG * C-state exit diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h index d45d51bedb87..032f3e3072ec 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.h +++ b/drivers/gpu/drm/i915/display/intel_dmc.h @@ -24,6 +24,8 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state); void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state); void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, bool block); +void intel_dmc_configure_dc_balance_ctl_regs(struct intel_display *display, + enum pipe pipe, bool enable); void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, enum pipe pipe, bool enable); void intel_dmc_fini(struct intel_display *display); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 8d7d19b86376..5eb4a7e97291 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -685,8 +685,10 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) if (crtc_state->cmrr.enable) ctl |= VRR_CTL_CMRR_ENABLE; - if (crtc_state->vrr.dc_balance.enable) + if (crtc_state->vrr.dc_balance.enable) { + intel_dmc_configure_dc_balance_ctl_regs(display, pipe, true); intel_pipedmc_dcb_enable(NULL, crtc); + } intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl); } @@ -702,8 +704,10 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) if (!old_crtc_state->vrr.enable) return; - if (old_crtc_state->vrr.dc_balance.enable) + if (old_crtc_state->vrr.dc_balance.enable) { intel_pipedmc_dcb_disable(NULL, crtc); + intel_dmc_configure_dc_balance_ctl_regs(display, pipe, false); + } ctl = trans_vrr_ctl(old_crtc_state); if (intel_vrr_always_use_vrr_tg(display)) -- 2.48.1
