> -----Original Message-----
> From: Borah, Chaitanya Kumar <[email protected]>
> Sent: Tuesday, April 8, 2025 4:30 PM
> To: [email protected]; [email protected]
> Cc: [email protected]; Shankar, Uma <[email protected]>;
> Borah, Chaitanya Kumar <[email protected]>; Manna, Animesh
> <[email protected]>
> Subject: [PATCH v2 09/11] drm/i915: Program DB LUT registers before vblank
>
> Double Buffered LUT registers can be programmed in the active region.
> This patch implements the MMIO path for it. Program the registers after
> evading
> vblank. The HW latches on to the registers after delayed vblank.
> It takes around 1024 cdclk cycles(~one scanline) for this.
>
> Following assumptions have been made while making this change
>
> - Current vblank evasion time is sufficient for programming
> the LUT registers.
> - Current guardband calculation would be sufficient for the HW
> to latch on to the new values
>
> v2: move loading LUTs to commit_pipe_post_planes() since a vblank
> evasion failure for this is probably less drastic than
> for plane programming. (Ville)
Looks Good to me.
Reviewed-by: Uma Shankar <[email protected]>
> Signed-off-by: Chaitanya Kumar Borah <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 58a84829fe58..398606f328e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6634,6 +6634,7 @@ static void commit_pipe_post_planes(struct
> intel_atomic_state *state,
> struct intel_display *display = to_intel_display(state);
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> + bool modeset = intel_crtc_needs_modeset(new_crtc_state);
>
> drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
>
> @@ -6642,10 +6643,15 @@ static void commit_pipe_post_planes(struct
> intel_atomic_state *state,
> * get a catastrophic underrun even if the two operations
> * end up happening in two different frames.
> */
> - if (DISPLAY_VER(display) >= 9 &&
> - !intel_crtc_needs_modeset(new_crtc_state))
> + if (DISPLAY_VER(display) >= 9 && !modeset)
> skl_detach_scalers(NULL, new_crtc_state);
>
> + if (!modeset &&
> + intel_crtc_needs_color_update(new_crtc_state) &&
> + !intel_color_uses_dsb(new_crtc_state) &&
> + HAS_DOUBLE_BUFFERED_LUT(display))
> + intel_color_load_luts(new_crtc_state);
> +
> if (intel_crtc_vrr_enabling(state, crtc))
> intel_vrr_enable(new_crtc_state);
> }
> --
> 2.25.1
