Disable Early Read and Src Swap (bit 14) by setting the chicken register. BSpec: 46045,52890
v2: Follow the Bspec implementation for the WA. v3: Have 2 separate defines for bit 14 and 15. - Rename register definitions with TGL_ prefix v4: Bspec changed. Again. Add WA to rcs_ WA list. Cc: Daniele Ceraolo Spurio <[email protected]> Cc: Matt Roper <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Reviewed-by: Matt Atwood <[email protected]> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 61106129287f..310f8e1beaab 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1326,6 +1326,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { struct drm_i915_private *i915 = engine->i915; + if (IS_TGL_REVID(i915, TGL_REVID_A0, REVID_FOREVER)) { + /* Wa_1606931601:tgl */ + wa_write_or(wal, + GEN7_ROW_CHICKEN2, + GEN12_EARLY_READ_SRC0_DISABLE); + } if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { /* Wa_1606700617:tgl */ wa_masked_en(wal, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0bd431f6a011..c46bec8ebd17 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9151,6 +9151,7 @@ enum { #define DOP_CLOCK_GATING_DISABLE (1 << 0) #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) +#define GEN12_EARLY_READ_SRC0_DISABLE (1 << 14) #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) -- 2.25.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
