On Fri, Jan 31, 2020 at 03:17:05PM -0800, Anusha Srivatsa wrote:
> Disable Early Read and Src Swap (bit 14) by setting the chicken
> register.
>
> BSpec: 46045,52890
>
> v2: Follow the Bspec implementation for the WA.
> v3: Have 2 separate defines for bit 14 and 15.
> - Rename register definitions with TGL_ prefix
> v4: Bspec changed. Again. Add WA to rcs_ WA list.
>
> Cc: Daniele Ceraolo Spurio <[email protected]>
> Cc: Matt Roper <[email protected]>
See whitespace fix,
Reviewed-by: Matt Atwood <[email protected]>
> Signed-off-by: Anusha Srivatsa <[email protected]>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 8d7c3191137c..b0bcf8c55da0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -593,6 +593,7 @@ static void tgl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> FF_MODE2_TDS_TIMER_MASK);
> +
^extra new line
> }
>
> static void
> @@ -1319,6 +1320,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
>
> + if (IS_TGL_REVID(i915, TGL_REVID_A0, REVID_FOREVER)) {
> + /* Wa_1606931601:tgl */
> + wa_write_or(wal,
> + GEN7_ROW_CHICKEN2,
> + GEN12_EARLY_READ_SRC0_DISABLE);
> + }
> if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> /* Wa_1606700617:tgl */
> wa_masked_en(wal,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0bd431f6a011..c46bec8ebd17 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9151,6 +9151,7 @@ enum {
> #define DOP_CLOCK_GATING_DISABLE (1 << 0)
> #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
> +#define GEN12_EARLY_READ_SRC0_DISABLE (1 << 14)
>
> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
> --
> 2.25.0
>
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