Disable Inter and intra Read Suppression (bit 15) and Early Read and Src Swap (bit 14) by setting the chicken register.
BSpec: 46045,52890 v2: Follow the Bspec implementation for the WA. v3: Have 2 separate defines for bit 14 and 15. - Rename register definitions with TGL_ prefix Cc: Matt Roper <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 5a7db279f702..1f84cd595f88 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -593,6 +593,12 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 : FF_MODE2_TDS_TIMER_MASK); + + /* Wa_1606931601:tgl */ + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, + GEN12_EARLY_READ_SRC0_DISABLE | + GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE); + } static void diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4c72b8ac0f2e..70ead809c706 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9149,6 +9149,8 @@ enum { #define DOP_CLOCK_GATING_DISABLE (1 << 0) #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) +#define GEN12_EARLY_READ_SRC0_DISABLE (1 << 14) +#define GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE (1 << 15) #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) -- 2.25.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
