Hi All,
Renaming a net or bus can already be implemented
with existing Gschem/Gnetlist/SCM code.
1) net/bus names connected to symbol_pinnumber
do not have to use the same name. e.g,
"net/busname=abus[31:0],a,b,c" can connect to
any net/bus pin of a symbol whose pinnumber
can be "BBUS[0:16],C,D,A ...".
2) If net/bus has to be renamed, an "Alias symbol"
(a tiny arrow or whatever you choose) connecting
2 net/bus, rename the net/bus. If you want to use
BUS-ripper to accomplish this, create you own
special BUS-ripper to accomplish it in your own
gnet-xxx.scm.
|-------
| Symbol
ABUS[0:31],r/w BBUS[31:0],rdw |
-----------------<>> ---------------| A[15:0],B[16:32]
^ |
(Alias symbol) | |
|---------
This is important, because each backend may do it
differently. Each gnet-xxx.scm can handle this
according to its own rule; just like how I/O ports
symbol are handled according to each backend rule.
e.g., VHDL
has specific rule how Alias are used.
By not imposing how netnames can be renamed, we
can have all the flexibilities. No Gschem/Gnetlist
C/SCM codes need to be changed to accomplish this.
Best Regards,
Paul Tan
-----Original Message-----
From: John Griessen <[email protected]>
To: gEDA developer mailing list <[email protected]>
Sent: Thu, 8 Jan 2009 7:53 pm
Subject: Re: gEDA-dev: Google Summer of Code 2009
Paul Tan wrote:
> Is it necessary that Gschem and/or Gnetlist
> C/SCM has to changed to accomodates your way
> of implementation? (except the visual BUS part)
.
.
.
> From: Steve Meier <[email protected]>
.
.
.
> 2) I am able to re-netname (this is a new verb) a bus at a bus to
> symbol interface or a bus to bus ripper interface (my bus rippers can
be
> either bus to net or bus to bus) as long as I keep the same names.
This
> means that by symbols don't have to be forced to a standard.
Steve is adding something new here it seems, so change is probably
needed to get
it..
I get a vision of top level netnames overriding, so the bus to pins
connections
of sub modules are all that determines the netlist. Renaming is the
thing that
is new and not done before
as far as I can see. I"m interested to hear more about the re-netnaming
concept.
With chip design style netnaming, you can20use a wires only module to
rearrange
and change names. Starting with
a bus called add-io-data<0:28>, you can plug it into a module that does
nothing
but rename and has straight through wires, maybe
with different groupings.
Then the outputs have new names. The top level names in the hierarchy
are still
going to be part of the netlist, so you could use
them as the netnames. A bus ripper sounds like a wires only module to
me. Am I
warm?
John Griessen
--
Ecosensory Austin TX
_______________________________________________
geda-dev mailing list
[email protected]
http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
_______________________________________________
geda-dev mailing list
[email protected]
http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
