On Sun, May 18, 2014 at 11:13 PM, shmeel gutl <shmeelg...@shmuelhome.mine.nu> wrote: > Are there hooks in gcc to deal with negative latencies? In other words, an > architecture that permits an instruction to use a result from an instruction > that will be issued later.
Do you mean bypasses? If so there is a bypass feature which you can use: https://gcc.gnu.org/onlinedocs/gccint/Processor-pipeline-description.html#index-data-bypass-3773 Thanks, Andrew Pinski > > At first glance it seems that it will will break a few things. > 1) The definition of dependencies cannot come from the simple ordering of > rtl. > 2) The scheduling problem starts to look like "get off the train 3 stops > before me". > 3) The definition of live ranges needs to use actual instruction timing > information, not just instruction sequencing. > > The hooks in the scheduler seem to be enough to stop damage but not enough > to take advantage of this "feature". > > Thanks >
