On 21-May-14 06:30 PM, Vladimir Makarov wrote:
I am just curious what happens when you put
insn2, insn1.
and insn2 uses a result of insn1 in 6 cycles and insn1 producing the
result in 3 cycles, but there are not ready functional units (e.g.
arithmentic units) necessary for insn1 for 4 or more cycles. It is
quite not trivial to guarantee that everything will be okay in general
case if you put insn2 before insn1.
This is not a problem for this architecture. The units are fully
pipelined and the only conflicts are in the first stage, during
instruction issue. That is, the vliw must be legal. The gcc dfa handles
this case fine.
