On Thu, Jul 16, 2026 at 06:20:26AM -0500, Vijay Shankar wrote:
> Split the movxo pattern into DMF and non-DMF variants.
>
> Use DMF move instructions (dmxxinstdmr512, dmmr, and dmxxextfdmr512)
> for accumulator/DMR moves while retaining the existing split for
> non-DMR operands.
>
> 2026-07-15 Vijay Shankar <[email protected]>
The movxo_dmf insn is wrong. You used the old %Y<n> print_operand
format, when you should use %W<n>. If I compile:
#ifndef TYPE
#define TYPE __vector_quad
#endif
#ifdef USE_VSX
#define CONSTRAINT "wa"
#else
#define CONSTRAINT "wD"
#endif
void copy (TYPE *p, TYPE *q) { *p = *q; }
void do_asm (TYPE *p, TYPE *q) { TYPE x = *p; __asm__(" # %A0" : "+"
CONSTRAINT (x)); *q = x; }
with -O2 -mregnames -mcpu=future, I get:
foo-dmf2.s: Assembler messages:
foo-dmf2.s:34: Warning: invalid register expression
foo-dmf2.s:40: Warning: invalid register expression
The two asm lines are:
dmxxinstdmr512 %dm0,%vs0,%f2,0
and
dmxxextfdmr512 %vs0,%f2,%dm0,0
> gcc/ChangeLog:
> * config/rs6000/mma.md (*movxo): renamed to movxo_nodmf
> (*movxo_nodmf): updated contraint to use wD and add !TARGET_DMF
> (*movxo_dmf): New pattern to handle dmf insert/extract from vsx
> ---
> gcc/config/rs6000/mma.md | 33 +++++++++++++++++++++++++++++----
> 1 file changed, 29 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
> index 1fadc5cd886..2c0ddc280a2 100644
> --- a/gcc/config/rs6000/mma.md
> +++ b/gcc/config/rs6000/mma.md
> @@ -341,10 +341,10 @@ (define_expand "movxo"
> gcc_assert (false);
> })
>
> -(define_insn_and_split "*movxo"
> - [(set (match_operand:XO 0 "nonimmediate_operand" "=d,ZwO,d")
> - (match_operand:XO 1 "input_operand" "ZwO,d,d"))]
> - "TARGET_MMA
> +(define_insn_and_split "*movxo_nodmf"
> + [(set (match_operand:XO 0 "nonimmediate_operand" "=wD,ZwO,wD")
> + (match_operand:XO 1 "input_operand" "ZwO,wD,wD"))]
> + "TARGET_MMA && !TARGET_DMF
> && (gpc_reg_operand (operands[0], XOmode)
> || gpc_reg_operand (operands[1], XOmode))"
> "@
> @@ -361,6 +361,31 @@ (define_insn_and_split "*movxo"
> (set_attr "length" "*,*,16")
> (set_attr "max_prefixed_insns" "2,2,*")])
>
> +(define_insn_and_split "*movxo_dmf"
> + [(set (match_operand:XO 0 "nonimmediate_operand" "=wa,ZwO,wa,wD,wD,wa")
> + (match_operand:XO 1 "input_operand" "ZwO,wa, wa,wa,wD,wD"))]
> + "TARGET_DMF
> + && (gpc_reg_operand (operands[0], XOmode)
> + || gpc_reg_operand (operands[1], XOmode))"
> + "@
> + #
> + #
> + #
> + dmxxinstdmr512 %0,%x1,%Y1,0
> + dmmr %0,%1
> + dmxxextfdmr512 %x0,%Y0,%1,0"
> + "&& reload_completed
> + && !dmr_register_operand (operands[0], XOmode)
> + && !dmr_register_operand (operands[1], XOmode)"
> + [(const_int 0)]
> +{
> + rs6000_split_multireg_move (operands[0], operands[1]);
> + DONE;
> +}
> + [(set_attr "type" "vecload,vecstore,veclogical,dmf,dmf,dmf")
> + (set_attr "length" "*,*,16,*,*,*")
> + (set_attr "max_prefixed_insns" "2,2,*,*,*,*")])
> +
> (define_expand "vsx_assemble_pair"
> [(match_operand:OO 0 "vsx_register_operand")
> (match_operand:V16QI 1 "mma_assemble_input_operand")
> --
> 2.52.0
>
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: [email protected]
