On Thu, Jul 16, 2026 at 06:52:03PM +0530, Kishan Parmar wrote: > Add support for the DMF (Dense Math Facility) and MMA+ > (Matrix-Multiply Assist Plus) builtins and instructions which may be > available on a future Power processor. > > This patch extends the existing MMA infrastructure to support Dense > Math Registers (DMRs). > > Key changes: > > 1. Extended MMA operand support from 7 to 9 operands (MAX_MMA_OPERANDS) > > 2. Added new DMF-specific unspecs: > > * UNSPEC_DMF_DMXOR for DMR XOR operations > * UNSPEC_DMF_DMXVI8GERX4* for DMR GER (outer product) operations > * UNSPEC_DMF_PMDMXVI8GERX4* for prefixed DMR GER operations > * UNSPEC_DMF_DMSETDMRZ for zeroing a DMR register > > 3. Implemented new instruction patterns in mma.md: > > * dmf_build_dmr: Build a DMR from eight vector operands > * dmf_dmsetdmrz: Zero a DMR register > * dmf_dmxor: XOR operation on DMR registers > * dmf_dmxvi8gerx4/dmxvi8gerx4pp: DMR outer product operations > * dmf_pmdmxvi8gerx4/pmdmxvi8gerx4pp: Prefixed DMR outer product > operations > > 4. Added new DMF builtins and updated GIMPLE folding: > > * Added DMF and MMA+ builtins > * Updated GIMPLE folding to handle DMR pass-by-reference semantics > * Extended builtin expansion to support up to 9 operand instructions > > 5. Added documentation for the new DMF and MMA+ builtins. > > The implementation follows the existing MMA pattern where user-facing > builtins use pass-by-reference for DMR arguments, while internal > builtins use pass-by-value for optimization.
This looks ok for submission to the master branch. -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: [email protected]
