[PATCH 36/48] sparc: Fix typos in various files

[dhruvc]

From: Dhruv Chawla <dhr...@nvidia.com>

Signed-off-by: Dhruv Chawla <dhr...@nvidia.com>

gcc/ChangeLog:

        * config/sparc/freebsd.h: Fix typos.
        * config/sparc/sparc.cc (emit_scc_insn): Likewise.
        (sparc_emit_membar_for_model): Likewise.
---
 gcc/config/sparc/freebsd.h | 2 +-
 gcc/config/sparc/sparc.cc  | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/config/sparc/freebsd.h b/gcc/config/sparc/freebsd.h
index 4820150d1e4..162aed800e3 100644
--- a/gcc/config/sparc/freebsd.h
+++ b/gcc/config/sparc/freebsd.h
@@ -112,7 +112,7 @@ along with GCC; see the file COPYING3.  If not see
 /* DWARF bits.  */
 
 /* Follow Irix 6 and not the Dwarf2 draft in using 64-bit offsets.
-   Obviously the Dwarf2 folks havn't tried to actually build systems
+   Obviously the Dwarf2 folks haven't tried to actually build systems
    with their spec.  On a 64-bit system, only 64-bit relocs become
    RELATIVE relocations.  */
 
diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc
index 47783fdeed9..9b191ad492d 100644
--- a/gcc/config/sparc/sparc.cc
+++ b/gcc/config/sparc/sparc.cc
@@ -3578,7 +3578,7 @@ emit_scc_insn (rtx operands[])
       return true;
     }
 
-  /* All the posibilities to use addx/subx based sequences has been
+  /* All the possibilities to use addx/subx based sequences has been
      exhausted, try for a 3 instruction sequence using v9 conditional
      moves.  */
   if (TARGET_V9 && gen_v9_scc (operands[0], code, x, y))
@@ -12763,7 +12763,7 @@ sparc_emit_membar_for_model (enum memmodel model,
         are followed by an implied StoreStore.  */
       implied |= StoreStore;
 
-      /* If we're not looking for a raw barrer (before+after), then atomic
+      /* If we're not looking for a raw barrier (before+after), then atomic
         operations get the benefit of being both load and store.  */
       if (load_store == 3 && before_after == 1)
        implied |= StoreLoad;
@@ -12774,7 +12774,7 @@ sparc_emit_membar_for_model (enum memmodel model,
         are followed by an implied LoadLoad | LoadStore.  */
       implied |= LoadLoad | LoadStore;
 
-      /* If we're not looking for a raw barrer (before+after), then atomic
+      /* If we're not looking for a raw barrier (before+after), then atomic
         operations get the benefit of being both load and store.  */
       if (load_store == 3 && before_after == 2)
        implied |= StoreLoad | StoreStore;
-- 
2.43.0