From: Dhruv Chawla <[email protected]>
Signed-off-by: Dhruv Chawla <[email protected]>
gcc/ChangeLog:
* config/pa/pa.cc (pa_assemble_integer): Fix typos.
(pa_can_change_mode_class): Likewise.
libgcc/ChangeLog:
* config/pa/linux-atomic.c: Fix typos.
* config/pa/sync-libfuncs.c: Likewise.
---
gcc/config/pa/pa.cc | 4 ++--
libgcc/config/pa/linux-atomic.c | 2 +-
libgcc/config/pa/sync-libfuncs.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc
index beb5bba30b8..4ec234b448e 100644
--- a/gcc/config/pa/pa.cc
+++ b/gcc/config/pa/pa.cc
@@ -3627,7 +3627,7 @@ pa_assemble_integer (rtx x, unsigned int size, int
aligned_p)
/* When we have a SYMBOL_REF with a SYMBOL_REF_DECL, we need to call
call assemble_external and set the SYMBOL_REF_DECL to NULL before
calling output_addr_const. Otherwise, it may call assemble_external
- in the midst of outputing the assembler code for the SYMBOL_REF.
+ in the midst of outputting the assembler code for the SYMBOL_REF.
We restore the SYMBOL_REF_DECL after the output is done. */
if (GET_CODE (x) == SYMBOL_REF)
{
@@ -10527,7 +10527,7 @@ pa_can_change_mode_class (machine_mode from,
machine_mode to,
We should return FALSE for QImode and HImode because these modes
are not ok in the floating-point registers. However, this prevents
- tieing these modes to SImode and DImode in the general registers.
+ tying these modes to SImode and DImode in the general registers.
So, this isn't a good idea. We rely on TARGET_HARD_REGNO_MODE_OK and
TARGET_CAN_CHANGE_MODE_CLASS to prevent these modes from being used
in the floating-point registers. */
diff --git a/libgcc/config/pa/linux-atomic.c b/libgcc/config/pa/linux-atomic.c
index 65b97ab19a6..c0acb28502f 100644
--- a/libgcc/config/pa/linux-atomic.c
+++ b/libgcc/config/pa/linux-atomic.c
@@ -40,7 +40,7 @@ typedef long long unsigned int u64;
#endif
/* PA-RISC 2.0 supports out-of-order execution for loads and stores.
- Thus, we need to synchonize memory accesses. For more info, see:
+ Thus, we need to synchronize memory accesses. For more info, see:
"Advanced Performance Features of the 64-bit PA-8000" by Doug Hunt.
We implement byte, short and int versions of each atomic operation
diff --git a/libgcc/config/pa/sync-libfuncs.c b/libgcc/config/pa/sync-libfuncs.c
index 8442988d0a3..1a4d81c570c 100644
--- a/libgcc/config/pa/sync-libfuncs.c
+++ b/libgcc/config/pa/sync-libfuncs.c
@@ -35,7 +35,7 @@ typedef long long unsigned int u64;
#endif
/* PA-RISC 2.0 supports out-of-order execution for loads and stores.
- Thus, we need to synchonize memory accesses. For more info, see:
+ Thus, we need to synchronize memory accesses. For more info, see:
"Advanced Performance Features of the 64-bit PA-8000" by Doug Hunt. */
typedef volatile int __attribute__((aligned (16))) ldcw_t;
--
2.43.0
