From: Dhruv Chawla <[email protected]>
Signed-off-by: Dhruv Chawla <[email protected]>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_subset_list::add): Fix
typos.
(riscv_subset_list::parse_single_multiletter_ext): Likewise.
(riscv_subset_list::set_loc): Likewise.
(riscv_arch_str): Likewise.
* config/riscv/riscv-avlprop.cc: Likewise.
* config/riscv/riscv-bclr-lowest-set-bit.cc (find_later_ctz): Likewise.
* config/riscv/riscv-ext-andes.def: Likewise.
* config/riscv/riscv-ext.def: Likewise.
* config/riscv/riscv-profiles.def: Likewise.
* config/riscv/riscv-selftests.cc (run_const_vector_selftests):
Likewise.
(run_broadcast_selftests): Likewise.
(riscv_run_selftests): Likewise.
* config/riscv/riscv-string.cc (riscv_expand_strcmp): Likewise.
* config/riscv/riscv-v.cc (shuffle_decompress_patterns): Likewise.
(vls_mode_valid_p): Likewise.
* config/riscv/riscv-vect-permconst.cc (vector_permconst::process_bb):
Likewise.
* config/riscv/riscv-vector-builtins.cc
(riscv_pragma_intrinsic_flags_pollute): Likewise.
* config/riscv/riscv-vsetvl.cc: Likewise.
* config/riscv/riscv-zicfilp.cc: Likewise.
* config/riscv/riscv.cc (riscv_expand_mult_with_const_int): Likewise.
(riscv_rtx_costs): Likewise.
(riscv_address_cost): Likewise.
(riscv_vls_cc_function_abi): Likewise.
(riscv_frm_mode_needed): Likewise.
(dispatch_function_versions): Likewise.
* config/riscv/riscv.h (DWARF_REG_TO_UNWIND_COLUMN): Likewise.
* config/riscv/riscv.md: Likewise.
---
gcc/common/config/riscv/riscv-common.cc | 8 ++++----
gcc/config/riscv/riscv-avlprop.cc | 2 +-
gcc/config/riscv/riscv-bclr-lowest-set-bit.cc | 2 +-
gcc/config/riscv/riscv-ext-andes.def | 2 +-
gcc/config/riscv/riscv-ext.def | 2 +-
gcc/config/riscv/riscv-profiles.def | 2 +-
gcc/config/riscv/riscv-selftests.cc | 6 +++---
gcc/config/riscv/riscv-string.cc | 2 +-
gcc/config/riscv/riscv-v.cc | 4 ++--
gcc/config/riscv/riscv-vect-permconst.cc | 2 +-
gcc/config/riscv/riscv-vector-builtins.cc | 2 +-
gcc/config/riscv/riscv-vsetvl.cc | 4 ++--
gcc/config/riscv/riscv-zicfilp.cc | 2 +-
gcc/config/riscv/riscv.cc | 12 ++++++------
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/riscv.md | 10 +++++-----
16 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index b149393e35f..8d6997bd9f6 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -529,7 +529,7 @@ riscv_subset_list::add (const char *subset, int
major_version,
{
if (ext->implied_p)
{
- /* We won't add impiled `ext` if it already in list. */
+ /* We won't add implied `ext` if it already in list. */
gcc_assert (!implied_p);
ext->implied_p = implied_p;
ext->major_version = major_version;
@@ -1266,7 +1266,7 @@ riscv_subset_list::parse_single_multiletter_ext (const
char *p,
found_any_number = true;
continue;
}
- /* Might be version seperator, but need to check one more char,
+ /* Might be version separator, but need to check one more char,
we only allow <major>p<minor>, so we could stop parsing if found
any more `p`. */
if (subset[i] == 'p' &&
@@ -1425,7 +1425,7 @@ riscv_subset_list::set_loc (location_t *loc)
}
/* Make sure the implied or combined extension is included after add
- a new std extension to subset list or likewise. For exmaple as below,
+ a new std extension to subset list or likewise. For example as below,
void __attribute__((target("arch=+v"))) func () with -march=rv64gc.
@@ -1465,7 +1465,7 @@ riscv_arch_str (bool version_p)
{NAME, &gcc_options::VAR, &cl_target_option::VAR, MASK}
/* Mapping table between extension to internal flag,
- this table is not needed to add manually unless there is speical rule. */
+ this table is not needed to add manually unless there is special rule. */
static const riscv_extra_ext_flag_table_t riscv_extra_ext_flag_table[] =
{
RISCV_EXT_FLAG_ENTRY ("zve32x", x_riscv_isa_flags, MASK_VECTOR),
diff --git a/gcc/config/riscv/riscv-avlprop.cc
b/gcc/config/riscv/riscv-avlprop.cc
index a9aaf3f0cd3..d8cbda11cba 100644
--- a/gcc/config/riscv/riscv-avlprop.cc
+++ b/gcc/config/riscv/riscv-avlprop.cc
@@ -51,7 +51,7 @@ along with GCC; see the file COPYING3. If not see
tail elements are agnostic.
We DON'T do this optimization on VSETVL pass since it is a
- post-RA pass that consumed 't0' already wheras a standalone
+ post-RA pass that consumed 't0' already whereas a standalone
pre-RA AVL propagation pass allows us elide the consumption
of the pseudo register of 't0' then we can reduce scalar
register pressure.
diff --git a/gcc/config/riscv/riscv-bclr-lowest-set-bit.cc
b/gcc/config/riscv/riscv-bclr-lowest-set-bit.cc
index 99f15418cf7..ecfa511a882 100644
--- a/gcc/config/riscv/riscv-bclr-lowest-set-bit.cc
+++ b/gcc/config/riscv/riscv-bclr-lowest-set-bit.cc
@@ -164,7 +164,7 @@ find_later_ctz (rtx_insn *start, rtx src, int limit)
inserting unrelated instructions between the two components of
the x & (x - 1) idiom. We'd have to match the ctz in various
positions as well as deal with random insns the scheduler puts
- in the middle of the key instrutions.
+ in the middle of the key instructions.
So, this mini pass to optimize this scenario. */
diff --git a/gcc/config/riscv/riscv-ext-andes.def
b/gcc/config/riscv/riscv-ext-andes.def
index b4f7389a75e..7aa7852a792 100644
--- a/gcc/config/riscv/riscv-ext-andes.def
+++ b/gcc/config/riscv/riscv-ext-andes.def
@@ -24,7 +24,7 @@ Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */
DEFINE_RISCV_EXT(
/* NAME */ xandesperf,
/* UPPERCASE_NAME */ XANDESPERF,
- /* FULL_NAME */ "Andes performace extension",
+ /* FULL_NAME */ "Andes performance extension",
/* DESC */ "",
/* URL */ ,
/* DEP_EXTS */ ({}),
diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 71d34470848..e3300a14fc0 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -66,7 +66,7 @@ Format of DEFINE_RISCV_EXT:
Extra flags for the extension, this is a bitmask of the
extra flags. The extra flags are:
- EXT_FLAG_MACRO: Set this flag if this extension is just a macro of set of
- extensions, and not define any new instrcutions, new CSRs or new
+ extensions, and not define any new instructions, new CSRs or new
behaviors, the example is `b` extension is just a macro of `zba`, `zbb`
and `zbs`.
*/
diff --git a/gcc/config/riscv/riscv-profiles.def
b/gcc/config/riscv/riscv-profiles.def
index 783eef13722..7a5a15b285a 100644
--- a/gcc/config/riscv/riscv-profiles.def
+++ b/gcc/config/riscv/riscv-profiles.def
@@ -17,7 +17,7 @@
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
-/* This is a list of RISC-V Profiles defination.
+/* This is a list of RISC-V Profiles definitions.
Before using #include to read this file, define a macro:
diff --git a/gcc/config/riscv/riscv-selftests.cc
b/gcc/config/riscv/riscv-selftests.cc
index 1e91d2d6de6..d9fd6508254 100644
--- a/gcc/config/riscv/riscv-selftests.cc
+++ b/gcc/config/riscv/riscv-selftests.cc
@@ -247,7 +247,7 @@ run_poly_int_selftests (void)
static void
run_const_vector_selftests (void)
{
- /* We dont't need to do the redundant tests in different march && mabi.
+ /* We don't need to do the redundant tests in different march && mabi.
Just pick up the march && mabi which fully support all RVV modes. */
riscv_selftest_arch_abi_setter rv ("rv64imafdcv", ABI_LP64D);
rtl_dump_test t (SELFTEST_LOCATION, locate_file ("riscv/empty-func.rtl"));
@@ -319,7 +319,7 @@ run_const_vector_selftests (void)
static void
run_broadcast_selftests (void)
{
- /* We dont't need to do the redundant tests in different march && mabi.
+ /* We don't need to do the redundant tests in different march && mabi.
Just pick up the march && mabi which fully support all RVV modes. */
riscv_selftest_arch_abi_setter rv ("rv64imafdcv", ABI_LP64D);
rtl_dump_test t (SELFTEST_LOCATION, locate_file ("riscv/empty-func.rtl"));
@@ -532,7 +532,7 @@ riscv_run_selftests (void)
/* We can know POLY value = [4, 4] when BYTES_PER_RISCV_VECTOR
is !is_constant () since we can use csrr vlenb and scalar shift
instruction to compute such POLY value and store it into a scalar
- register. Wheras, we can't know [4, 4] on it is specified as
+ register. Whereas, we can't know [4, 4] on it is specified as
FIXED-VLMAX since BYTES_PER_RISCV_VECTOR = 16 for -march=rv64gcv
and csrr vlenb is 16 which is totally unrelated to any
compile-time unknown POLY value.
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index 51b98e4906c..e4f5c289f40 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -487,7 +487,7 @@ riscv_expand_strcmp (rtx result, rtx src1, rtx src2,
if (riscv_strcmp_inline_limit == 0)
return false;
- /* Round down the comparision limit to a multiple of xlen. */
+ /* Round down the comparison limit to a multiple of xlen. */
compare_max = riscv_strcmp_inline_limit & ~(xlen - 1);
/* Decide how many bytes to compare inline. */
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 88bff235f06..c2b2e346d0a 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -4087,7 +4087,7 @@ shuffle_decompress_patterns (struct expand_vec_perm_d *d)
poly_uint64 nelt = d->perm.length ();
machine_mode mask_mode = get_mask_mode (d->vmode);
- /* For constant size indices, we dont't need to handle it here.
+ /* For constant size indices, we don't need to handle it here.
Just leave it to vec_perm<mode>. */
if (d->perm.length ().is_constant ())
return false;
@@ -5309,7 +5309,7 @@ vls_mode_valid_p (machine_mode mode, bool
allow_up_to_lmul_8)
}
/* We don't have to convert the floating point to integer when the
- mantissa is zero. Thus, ther will be a limitation for both the
+ mantissa is zero. Thus, there will be a limitation for both the
single and double precision floating point. There will be no
mantissa if the floating point is greater than the limit.
diff --git a/gcc/config/riscv/riscv-vect-permconst.cc
b/gcc/config/riscv/riscv-vect-permconst.cc
index 1365c9d0f2e..34a4a9b97f4 100644
--- a/gcc/config/riscv/riscv-vect-permconst.cc
+++ b/gcc/config/riscv/riscv-vect-permconst.cc
@@ -177,7 +177,7 @@ vector_permconst::process_bb (basic_block bb)
continue;
/* A load from the constant pool should have a REG_EQUAL
- note with the vector contant in the note. */
+ note with the vector constant in the note. */
rtx note = find_reg_equal_equiv_note (insn);
if (!note
|| REG_NOTE_KIND (note) != REG_EQUAL
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index b3bce40e5bf..9e9e56b2f60 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3703,7 +3703,7 @@ riscv_pragma_intrinsic_flags_pollute (struct
pragma_intrinsic_flags *flags)
only need to pollute those flags that might affect the type registration.
e.g. zvfbmin and zvfhmin are required to define the vector bf16 and f16,
- and VECTOR_ELEN* also required for vector interger and floating
+ and VECTOR_ELEN* also required for vector integer and floating
type. */
flags->intrinsic_riscv_isa_flags = riscv_isa_flags;
flags->intrinsic_riscv_base_subext = riscv_base_subext;
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 2705e2a1717..16549c514dc 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -994,9 +994,9 @@ public:
E.g. BB 2 (Empty) ---> BB 3 (VALID, has rvv insn 1)
- BB 2 has empty VSETVL_INFO, wheras BB 3 has VSETVL_INFO that satisfies
+ BB 2 has empty VSETVL_INFO, whereas BB 3 has VSETVL_INFO that satisfies
get_insn ()->bb () == get_bb (). In earliest fusion, we may fuse bb 3 and
- bb 2 so that the 'get_bb ()' of BB2 VSETVL_INFO will be BB2 wheras the
+ bb 2 so that the 'get_bb ()' of BB2 VSETVL_INFO will be BB2 whereas the
'get_insn ()' of BB2 VSETVL INFO will be the rvv insn 1 (which is located
at BB3). */
bool insn_inside_bb_p () const { return get_insn ()->bb () == get_bb (); }
diff --git a/gcc/config/riscv/riscv-zicfilp.cc
b/gcc/config/riscv/riscv-zicfilp.cc
index 5cb6dd22830..de8a6f84216 100644
--- a/gcc/config/riscv/riscv-zicfilp.cc
+++ b/gcc/config/riscv/riscv-zicfilp.cc
@@ -53,7 +53,7 @@
When forward-CFI is disabled or unimplemented in the CPU, the
landing-pad check label instructions behave as NOP. When implemented in
the CPU, and enabled, the destination of an indirect branch must be
- LPAD insn. Otherwise, the CPU reaises an exception.
+ LPAD insn. Otherwise, the CPU raises an exception.
In order to enable this mechanism, this pass iterates through the
control flow of the code and adds appropriate LPAD instructions at the
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8a737bb41b6..e295d572e59 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3720,7 +3720,7 @@ riscv_expand_mult_with_const_int (machine_mode mode, rtx
dest, rtx multiplicand,
Essentially we want to generate (set (dest) (src)), where SRC is
a poly_int. We may need TMP as a scratch register. We assume TMP
- is truely a scratch register and need not have any particular value
+ is truly a scratch register and need not have any particular value
after the sequence. */
void
riscv_legitimize_poly_move (machine_mode mode, rtx dest, rtx tmp, rtx src)
@@ -4404,7 +4404,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBUTE_UN
instructions it needs. */
if ((cost = riscv_address_insns (XEXP (x, 0), mode, true)) > 0)
{
- /* When optimizing for size, make uncompressible 32-bit addresses
+ /* When optimizing for size, make incompressible 32-bit addresses
more expensive so that compressible 32-bit addresses are
preferred. */
if ((TARGET_RVC || TARGET_ZCA)
@@ -4898,7 +4898,7 @@ riscv_address_cost (rtx addr, machine_mode mode,
addr_space_t as ATTRIBUTE_UNUSED,
bool speed ATTRIBUTE_UNUSED)
{
- /* When optimizing for size, make uncompressible 32-bit addresses more
+ /* When optimizing for size, make incompressible 32-bit addresses more
* expensive so that compressible 32-bit addresses are preferred. */
if ((TARGET_RVC || TARGET_ZCA)
&& !speed && riscv_mshorten_memrefs && mode == SImode
@@ -7717,7 +7717,7 @@ riscv_vls_cc_function_abi (const_tree fntype, bool
check_only)
return riscv_get_vls_cc_attr (args);
}
-/* Implemention of TARGET_FNTYPE_ABI, but one extra parameter `check_only`
+/* Implementation of TARGET_FNTYPE_ABI, but one extra parameter `check_only`
to suppress warning message. */
static const predefined_function_abi &
@@ -13469,7 +13469,7 @@ riscv_frm_mode_needed (rtx_insn *cur_insn, int code)
{
if (!DYNAMIC_FRM_RTL(cfun))
{
- /* The dynamic frm will be initialized only onece during cfun. */
+ /* The dynamic frm will be initialized only once during cfun. */
DYNAMIC_FRM_RTL (cfun) = gen_reg_rtx (SImode);
emit_insn_at_entry (gen_frrmsi (DYNAMIC_FRM_RTL (cfun)));
CFUN_IN_CALL (cfun) = false;
@@ -14832,7 +14832,7 @@ dispatch_function_versions (tree dispatch_decl,
gseq = bb_seq (*empty_bb);
/* Function version dispatch is via IFUNC. IFUNC resolvers fire before
- constructors, so explicity call __init_riscv_feature_bits here. */
+ constructors, so explicitly call __init_riscv_feature_bits here. */
tree init_fn_type = build_function_type_list (void_type_node,
long_unsigned_type_node,
ptr_type_node,
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 57c5777c34d..fccf9e6dc09 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1284,7 +1284,7 @@ extern void riscv_remove_unneeded_save_restore_calls
(void);
#define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \
((REGNO == RISCV_DWARF_VLENB) ? (FIRST_PSEUDO_REGISTER + 1) : REGNO)
-/* Like s390, riscv also defined this macro for the vector comparision. Then
+/* Like s390, riscv also defined this macro for the vector comparison. Then
the simplify-rtx relational_result will canonicalize the result to the
CONST1_RTX for the simplification. */
#define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE))
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 8615a2ebad4..f308924c53f 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -362,7 +362,7 @@
;; rdvl vector length vl csrr read
;; wrvxrm vector fixed-point rounding mode write
;; wrfrm vector floating-point rounding mode write
-;; vsetvl vector configuration-setting instrucions
+;; vsetvl vector configuration-setting instructions
;; 7. Vector Loads and Stores
;; vlde vector unit-stride load instructions
;; vste vector unit-stride store instructions
@@ -489,11 +489,11 @@
;; vsm4r crypto vector SM4 Rounds instructions
;; vsm3me crypto vector SM3 Message Expansion instructions
;; vsm3c crypto vector SM3 Compression instructions
-;; 18.Vector BF16 instrctions
+;; 18.Vector BF16 instructions
;; vfncvtbf16 vector narrowing single floating-point to brain floating-point
instruction
;; vfwcvtbf16 vector widening brain floating-point to single floating-point
instruction
;; vfwmaccbf16 vector BF16 widening multiply-accumulate
-;; SiFive custom extension instrctions
+;; SiFive custom extension instructions
;; sf_vqmacc vector matrix integer multiply-add instructions
;; sf_vfnrclip vector fp32 to int8 ranged clip instructions
;; sf_vc vector coprocessor interface without side effect
@@ -3252,7 +3252,7 @@
;; Handle logical AND feeding an equality test against zero where an operand
;; to the AND is a constant requiring synthesis. Because we only care about
-;; zero/nonzero state afte the AND, we may be able to shift both operands
+;; zero/nonzero state after the AND, we may be able to shift both operands
;; of the AND to the right and eliminate the need for constant synthesis.
;;
;; Once mvconst_internal goes away, this likely turns into a simple splitter.
@@ -4814,7 +4814,7 @@
[(set_attr "type" "load")
(set (attr "length") (const_int 8))])
-;; The AND is redunant here. It always turns off the high 32 bits and the
+;; The AND is redundant here. It always turns off the high 32 bits and the
;; low number of bits equal to the shift count. Those upper 32 bits will be
;; reset by the SIGN_EXTEND at the end.
;;
--
2.43.0
