From: Dhruv Chawla <[email protected]>
Signed-off-by: Dhruv Chawla <[email protected]>
gcc/ChangeLog:
* common/config/arm/arm-common.cc (arm_config_default): Fix typos.
(arm_canon_arch_option_1): Likewise.
* config/arm/aarch-bti-insert.cc (rest_of_insert_bti): Likewise.
* config/arm/arm-builtins.cc (MAC_LANE_PAIR_QUALIFIERS): Likewise.
(USMAC_LANE_QUADTUP_QUALIFIERS): Likewise.
* config/arm/arm-modes.def (ADJUST_FLOAT_FORMAT): Likewise.
* config/arm/arm-mve-builtins-base.cc: Likewise.
* config/arm/arm-mve-builtins-shapes.cc (struct
binary_lshift_unsigned_def): Likewise.
(struct binary_maxamina_def): Likewise.
(struct viddup_def): Likewise.
(struct vidwdup_def): Likewise.
* config/arm/arm-protos.h (struct tune_params): Likewise.
* config/arm/arm.cc (arm_option_override_internal): Likewise.
(arm_option_override): Likewise.
(optimal_immediate_sequence_1): Likewise.
(arm_pcs_from_attribute): Likewise.
(aapcs_vfp_advance): Likewise.
(aapcs_layout_arg): Likewise.
(arm_init_cumulative_args): Likewise.
(arm_rtx_costs_internal): Likewise.
(mve_bool_vec_to_const): Likewise.
(operands_ok_ldrd_strd): Likewise.
(emit_multi_reg_push): Likewise.
(arm_emit_vfp_multi_reg_pop): Likewise.
(thumb2_emit_ldrd_pop): Likewise.
(arm_print_condition): Likewise.
(get_arm_condition_code): Likewise.
(thumb_pop): Likewise.
(arm_print_asm_arch_directives): Likewise.
(arm_debugger_regno): Likewise.
(arm_target_bb_ok_for_lob): Likewise.
(arm_mve_load_store_insn_p): Likewise.
(arm_mve_check_reg_origin_is_num_elems): Likewise.
(arm_mve_dlstp_check_dec_counter): Likewise.
(arm_mve_loop_valid_for_dlstp): Likewise.
(arm_loop_unroll_adjust): Likewise.
* config/arm/arm.h (ROUND_UP_WORD): Likewise.
* config/arm/arm.md: Likewise.
* config/arm/constraints.md: Likewise.
* config/arm/cortex-a17-neon.md: Likewise.
* config/arm/cortex-r4f.md: Likewise.
* config/arm/crypto.md: Likewise.
* config/arm/elf.h: Likewise.
* config/arm/fa726te.md: Likewise.
* config/arm/iterators.md: Likewise.
* config/arm/neon.md: Likewise.
* config/arm/thumb1.md: Likewise.
* config/arm/uclinuxfdpiceabi.h: Likewise.
* config/arm/unspecs.md: Likewise.
* config/arm/vec-common.md: Likewise.
* config/arm/vxworks.h (STACK_CHECK_PROTECT): Likewise.
libgcc/ChangeLog:
* config/arm/fp16.c (__gnu_float2h_internal): Fix typos.
---
gcc/common/config/arm/arm-common.cc | 12 ++---
gcc/config/arm/aarch-bti-insert.cc | 2 +-
gcc/config/arm/arm-builtins.cc | 4 +-
gcc/config/arm/arm-modes.def | 2 +-
gcc/config/arm/arm-mve-builtins-base.cc | 4 +-
gcc/config/arm/arm-mve-builtins-shapes.cc | 8 ++--
gcc/config/arm/arm-protos.h | 2 +-
gcc/config/arm/arm.cc | 54 +++++++++++------------
gcc/config/arm/arm.h | 2 +-
gcc/config/arm/arm.md | 8 ++--
gcc/config/arm/constraints.md | 2 +-
gcc/config/arm/cortex-a17-neon.md | 2 +-
gcc/config/arm/cortex-r4f.md | 2 +-
gcc/config/arm/crypto.md | 4 +-
gcc/config/arm/elf.h | 2 +-
gcc/config/arm/fa726te.md | 2 +-
gcc/config/arm/iterators.md | 4 +-
gcc/config/arm/neon.md | 2 +-
gcc/config/arm/thumb1.md | 4 +-
gcc/config/arm/uclinuxfdpiceabi.h | 2 +-
gcc/config/arm/unspecs.md | 2 +-
gcc/config/arm/vec-common.md | 2 +-
gcc/config/arm/vxworks.h | 2 +-
libgcc/config/arm/fp16.c | 2 +-
24 files changed, 66 insertions(+), 66 deletions(-)
diff --git a/gcc/common/config/arm/arm-common.cc
b/gcc/common/config/arm/arm-common.cc
index 24d78697a33..00ed0d85060 100644
--- a/gcc/common/config/arm/arm-common.cc
+++ b/gcc/common/config/arm/arm-common.cc
@@ -272,10 +272,10 @@ arm_config_default (const char *name)
/* Called by the driver to check whether the target denoted by current
command line options is a Thumb-only, or ARM-only, target. ARGV is
- an array of tupples (normally only one) where the first element of
- the tupple is 'cpu' or 'arch' and the second is the option passed
- to the compiler for that. An architecture tupple is always taken
- in preference to a cpu tupple and the last of each type always
+ an array of tuples (normally only one) where the first element of
+ the tuple is 'cpu' or 'arch' and the second is the option passed
+ to the compiler for that. An architecture tuple is always taken
+ in preference to a cpu tuple and the last of each type always
overrides any earlier setting. */
const char *
@@ -794,13 +794,13 @@ arm_canon_arch_option_1 (int argc, const char **argv,
bool arch_for_multilib)
/* If we have a soft-float ABI, disable the FPU. */
if (abi && strcmp (abi, "soft") == 0)
{
- /* Clearing the VFPv2 bit is sufficient to stop any extention that
+ /* Clearing the VFPv2 bit is sufficient to stop any extension that
builds on the FPU from matching. */
bitmap_clear_bit (target_isa, isa_bit_vfpv2);
}
/* Here we remove feature isa bits from -mlibarch string which are not
- necessary for multilib string comparsion. */
+ necessary for multilib string comparison. */
if ((arch || cpu) && arch_for_multilib)
{
const enum isa_feature removable_bits[] = {ISA_IGNORE_FOR_MULTILIB,
diff --git a/gcc/config/arm/aarch-bti-insert.cc
b/gcc/config/arm/aarch-bti-insert.cc
index b606a86e8fd..8d23eae77af 100644
--- a/gcc/config/arm/aarch-bti-insert.cc
+++ b/gcc/config/arm/aarch-bti-insert.cc
@@ -138,7 +138,7 @@ rest_of_insert_bti (void)
}
/* There could still be more labels that are valid targets of a
- BTI J instuction. To find them we start looking through the
+ BTI J instruction. To find them we start looking through the
JUMP_INSN. If it jumps to a jump table, then we find all labels
of the jump table to protect with a BTI J. */
if (JUMP_P (insn))
diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc
index 2a9cdea6c79..ee5c6041fec 100644
--- a/gcc/config/arm/arm-builtins.cc
+++ b/gcc/config/arm/arm-builtins.cc
@@ -139,7 +139,7 @@ arm_mac_lane_pair_qualifiers[SIMD_MAX_BUILTIN_ARGS]
qualifier_none, qualifier_lane_pair_index };
#define MAC_LANE_PAIR_QUALIFIERS (arm_mac_lane_pair_qualifiers)
-/* unsigned T (unsigned T, unsigned T, unsigend T, lane index). */
+/* unsigned T (unsigned T, unsigned T, unsigned T, lane index). */
static enum arm_type_qualifiers
arm_umac_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
@@ -153,7 +153,7 @@ arm_usmac_lane_quadtup_qualifiers[SIMD_MAX_BUILTIN_ARGS]
qualifier_none, qualifier_lane_quadtup_index };
#define USMAC_LANE_QUADTUP_QUALIFIERS (arm_usmac_lane_quadtup_qualifiers)
-/* T (T, T, unsigend T, lane index). */
+/* T (T, T, unsigned T, lane index). */
static enum arm_type_qualifiers
arm_sumac_lane_quadtup_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none,
diff --git a/gcc/config/arm/arm-modes.def b/gcc/config/arm/arm-modes.def
index ac7c5ca173c..612f7006d1c 100644
--- a/gcc/config/arm/arm-modes.def
+++ b/gcc/config/arm/arm-modes.def
@@ -43,7 +43,7 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format ==
ARM_FP16_FORMAT_ALTERNATIVE)
(eg after an unsigned borrow with carry-in propagation).
(used for DImode signed comparisons).
CC_ADCmode is used when the carry is formed from the output of ADC for an
- addtion. In this case we cannot use the trick of comparing the sum
+ addition. In this case we cannot use the trick of comparing the sum
against one of the other operands.
CCmode should be used otherwise. */
diff --git a/gcc/config/arm/arm-mve-builtins-base.cc
b/gcc/config/arm/arm-mve-builtins-base.cc
index eaac4316d6b..0fbe0d986ad 100644
--- a/gcc/config/arm/arm-mve-builtins-base.cc
+++ b/gcc/config/arm/arm-mve-builtins-base.cc
@@ -753,7 +753,7 @@ public:
/* Map the vidup / vddup function directly to CODE (UNSPEC, M) where M is the
vector mode associated with type suffix 0. We need this special case
- because in MODE_wb the builtins derefrence the first parameter and update
+ because in MODE_wb the builtins dereference the first parameter and update
its contents. We also have to insert the two additional parameters needed
by the builtins compared to the intrinsics. In wrapping mode, we have to
match the 'hack' to make sure the 'wrap' parameters is in odd register. */
@@ -886,7 +886,7 @@ public:
/* Map the vshlc function directly to CODE (UNSPEC, M) where M is the vector
mode associated with type suffix 0. We need this special case because the
- intrinsics derefrence the second parameter and update its contents. */
+ intrinsics dereference the second parameter and update its contents. */
class vshlc_impl : public function_base
{
public:
diff --git a/gcc/config/arm/arm-mve-builtins-shapes.cc
b/gcc/config/arm/arm-mve-builtins-shapes.cc
index 172e43dafa2..adc0dfc9784 100644
--- a/gcc/config/arm/arm-mve-builtins-shapes.cc
+++ b/gcc/config/arm/arm-mve-builtins-shapes.cc
@@ -702,7 +702,7 @@ struct binary_lshift_unsigned_def : public
overloaded_base<0>
if (r.pred == PRED_m)
{
/* With PRED_m, check that the 'inactive' first argument has
- the expeected unsigned type. */
+ the expected unsigned type. */
type_suffix_index return_type
= find_type_suffix (TYPE_unsigned, type_suffixes[type].element_bits);
@@ -750,7 +750,7 @@ struct binary_maxamina_def : public overloaded_base<0>
|| (type = r.infer_vector_type (i)) == NUM_TYPE_SUFFIXES)
return error_mark_node;
- /* Check that the first argument has the expeected unsigned
+ /* Check that the first argument has the expected unsigned
type. */
type_suffix_index return_type
= find_type_suffix (TYPE_unsigned, type_suffixes[type].element_bits);
@@ -2858,7 +2858,7 @@ struct viddup_def : public overloaded_base<0>
return error_mark_node;
type_suffix = r.type_suffix_ids[0];
- /* With PRED_m, ther is no type suffix, so infer it from the first
(inactive)
+ /* With PRED_m, there is no type suffix, so infer it from the first
(inactive)
argument. */
if (type_suffix == NUM_TYPE_SUFFIXES)
type_suffix = r.infer_vector_type (0);
@@ -2943,7 +2943,7 @@ struct vidwdup_def : public overloaded_base<0>
return error_mark_node;
type_suffix = r.type_suffix_ids[0];
- /* With PRED_m, ther is no type suffix, so infer it from the first
(inactive)
+ /* With PRED_m, there is no type suffix, so infer it from the first
(inactive)
argument. */
if (type_suffix == NUM_TYPE_SUFFIXES)
type_suffix = r.infer_vector_type (0);
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index cbfb473037c..b607cdb3fcc 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -360,7 +360,7 @@ struct tune_params
prefer_constant_pool: 1;
/* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */
enum {PREF_LDRD_FALSE, PREF_LDRD_TRUE} prefer_ldrd_strd: 1;
- /* The preference for non short cirtcuit operation when optimizing for
+ /* The preference for non short circuit operation when optimizing for
performance. The first element covers Thumb state and the second one
is for ARM state. */
enum log_op_non_short_circuit {LOG_OP_NON_SHORT_CIRCUIT_FALSE,
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 41808e42ab1..6ebe0a73e16 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -3137,7 +3137,7 @@ arm_option_override_internal (struct gcc_options *opts,
if (TARGET_THUMB_P (opts->x_target_flags) && TARGET_CALLEE_INTERWORKING)
opts->x_target_flags |= MASK_INTERWORK;
- /* need to remember initial values so combinaisons of options like
+ /* need to remember initial values so combinations of options like
-mflip-thumb -mthumb -fno-schedule-insns work for any attribute. */
cl_optimization *to = TREE_OPTIMIZATION (init_optimize);
@@ -3196,7 +3196,7 @@ arm_option_override_internal (struct gcc_options *opts,
'Find out how many of the (return) argument registers we can corrupt'.
As a consequence, the epilogue may clobber registers without fipa-ra
finding out about it. Therefore, disable fipa-ra in Thumb1 mode.
- TODO: Accurately model clobbers for epilogue_insns and reenable
+ TODO: Accurately model clobbers for epilogue_insns and re-enable
fipa-ra. */
if (TARGET_THUMB1_P (opts->x_target_flags))
opts->x_flag_ipa_ra = 0;
@@ -3869,7 +3869,7 @@ arm_option_override (void)
&& (!arm_arch7 || !current_tune->prefer_ldrd_strd))
flag_schedule_fusion = 0;
- /* Need to remember initial options before they are overriden. */
+ /* Need to remember initial options before they are overridden. */
init_optimize = build_optimization_node (&global_options,
&global_options_set);
@@ -4991,7 +4991,7 @@ optimal_immediate_sequence_1 (enum rtx_code code,
unsigned HOST_WIDE_INT val,
else if (loc > 16)
{
/* The 8-bit immediate already found clears b2 (and maybe b3)
- and we don't get here unless b1 is alredy clear, but it will
+ and we don't get here unless b1 is already clear, but it will
leave b4 unchanged. */
/* If we can clear b2 and b4 at once, then we win, since the
@@ -6305,7 +6305,7 @@ arm_pcs_from_attribute (tree attr)
}
/* Get the PCS variant to use for this call. TYPE is the function's type
- specification, DECL is the specific declartion. DECL may be null if
+ specification, DECL is the specific declaration. DECL may be null if
the call could be indirect or if this is a library call. */
static enum arm_pcs
arm_get_pcs_model (const_tree type, const_tree decl ATTRIBUTE_UNUSED)
@@ -6895,7 +6895,7 @@ aapcs_vfp_advance (CUMULATIVE_ARGS *pcum
ATTRIBUTE_UNUSED,
}
/* Table of co-processors that can be used to pass arguments in
- registers. Idealy no arugment should be a candidate for more than
+ registers. Ideally no argument should be a candidate for more than
one co-processor table entry, but the table is processed in order
and stops after the first match. If that entry then fails to put
the argument into a co-processor register, the argument will go on
@@ -7158,7 +7158,7 @@ aapcs_layout_arg (CUMULATIVE_ARGS *pcum, machine_mode
mode,
/* C6 - NCRN is set to 4. */
pcum->aapcs_next_ncrn = NUM_ARG_REGS;
- /* C7,C8 - arugment goes on the stack. We have nothing to do here. */
+ /* C7,C8 - argument goes on the stack. We have nothing to do here. */
return;
}
@@ -7218,7 +7218,7 @@ arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree
fntype,
Return 1 if double word alignment is required for argument passing.
Return -1 if double word alignment used to be required for argument
passing before PR77728 ABI fix, but is not required anymore.
- Return 0 if double word alignment is not required and wasn't requried
+ Return 0 if double word alignment is not required and wasn't required
before either. */
static int
arm_needs_doubleword_align (machine_mode mode, const_tree type)
@@ -10491,7 +10491,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum
rtx_code outer_code,
*cost = LIBCALL_COST (2);
/* Make the cost of sdiv more expensive so when both sdiv and udiv are
- possible udiv is prefered. */
+ possible udiv is preferred. */
*cost += (code == DIV ? COSTS_N_INSNS (1) : 0);
return false; /* All arguments must be in registers. */
@@ -10516,7 +10516,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum
rtx_code outer_code,
/* Fall-through. */
case UMOD:
/* Make the cost of sdiv more expensive so when both sdiv and udiv are
- possible udiv is prefered. */
+ possible udiv is preferred. */
*cost = LIBCALL_COST (2) + (code == MOD ? COSTS_N_INSNS (1) : 0);
return false; /* All arguments must be in registers. */
@@ -13394,7 +13394,7 @@ mve_bool_vec_to_const (rtx const_vec)
}
/* Return a non-NULL RTX iff VALS, which is a PARALLEL containing only
- constants (for vec_init) or CONST_VECTOR, can be effeciently loaded
+ constants (for vec_init) or CONST_VECTOR, can be efficiently loaded
into a register.
If this is the case, and GENERATE is set, we also generate code to do
@@ -17024,7 +17024,7 @@ operands_ok_ldrd_strd (rtx rt, rtx rt2, rtx rn,
HOST_WIDE_INT offset,
|| (t % 2 != 0) /* First destination register is not even. */
|| (t2 != t + 1)
/* PC can be used as base register (for offset addressing only),
- but it is depricated. */
+ but it is deprecated. */
|| (n == PC_REGNUM)))
return false;
@@ -22379,8 +22379,8 @@ emit_multi_reg_push (unsigned long mask, unsigned long
dwarf_regs_mask)
of dwarf code emitter and it doesn't consider reg-reg copies while
updating the register list. When PACBTI is enabled we manually
updated the .save directive register list to use "ra_auth_code"
- (pseduo register 143) instead of IP register as shown in following
- pseduo code.
+ (pseudo register 143) instead of IP register as shown in following
+ pseudo code.
Example:
pacbti ip, lr, sp
.cfi_register 143, 12
@@ -22643,7 +22643,7 @@ arm_emit_vfp_multi_reg_pop (int first_reg, int
num_regs, rtx base_reg)
par = emit_insn (par);
REG_NOTES (par) = dwarf;
- /* Make sure cfa doesn't leave with IP_REGNUM to allow unwinding fron FP. */
+ /* Make sure cfa doesn't leave with IP_REGNUM to allow unwinding from FP. */
if (REGNO (base_reg) == IP_REGNUM)
{
RTX_FRAME_RELATED_P (par) = 1;
@@ -22798,7 +22798,7 @@ thumb2_emit_ldrd_pop (unsigned long saved_regs_mask)
/* LDRD in ARM mode needs consecutive registers as operands. This function
emits LDRD whenever possible, otherwise it emits single-word loads. It uses
- offset addressing and then generates one separate stack udpate. This
provides
+ offset addressing and then generates one separate stack update. This
provides
more scheduling freedom, compared to writeback on every load. However,
if the function returns using load into PC directly
(i.e., if PC is in SAVED_REGS_MASK), the stack needs to be updated
@@ -24102,7 +24102,7 @@ arm_print_condition (FILE *stream)
/* Globally reserved letters: acln
- Puncutation letters currently used: @_-|?().!#
+ Punctuation letters currently used: @_-|?().!#
Lower case letters currently used: bcdefhimpqtvwxyz
Upper case letters currently used: ABCDEFGHIJKLMOPQRSTUV
Letters previously used, but now deprecated/obsolete: sNWXYZ.
@@ -25317,7 +25317,7 @@ get_arm_condition_code (rtx comparison)
}
/* Implement TARGET_FIXED_CONDITION_CODE_REGS. We only have condition
- code registers when not targetting Thumb1. The VFP condition register
+ code registers when not targeting Thumb1. The VFP condition register
only exists when generating hard-float code. */
static bool
arm_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
@@ -26278,7 +26278,7 @@ thumb_pop (FILE *f, unsigned long mask)
if (TARGET_INTERWORK || TARGET_BACKTRACE || crtl->calls_eh_return
|| IS_CMSE_ENTRY (arm_current_func_type ()))
{
- /* The PC is never poped directly, instead
+ /* The PC is never popped directly, instead
it is popped into r3 and then BX is used. */
fprintf (f, "}\n");
@@ -28614,7 +28614,7 @@ arm_print_asm_arch_directives (FILE *stream,
cl_target_option *targ_options)
if (strcmp (build_target.arch_name, "armv7ve") == 0)
{
- /* Keep backward compatability for assemblers which don't support
+ /* Keep backward compatibility for assemblers which don't support
armv7ve. Fortunately, none of the following extensions are reset
by a .fpu directive. */
asm_fprintf (stream, "\t.arch armv7-a\n");
@@ -29852,7 +29852,7 @@ arm_debugger_regno (unsigned int regno)
}
/* Dwarf models VFPv3 registers as 32 64-bit registers.
- GCC models tham as 64 32-bit registers, so we need to describe this to
+ GCC models them as 64 32-bit registers, so we need to describe this to
the DWARF generation code. Other registers can use the default. */
static rtx
arm_dwarf_register_span (rtx rtl)
@@ -34428,7 +34428,7 @@ arm_target_bb_ok_for_lob (basic_block bb)
&& single_succ_edge (bb)->dest == single_pred_edge (bb)->src);
}
-/* Utility fuction: Given a VCTP or a VCTP_M insn, return the number of MVE
+/* Utility function: Given a VCTP or a VCTP_M insn, return the number of MVE
lanes based on the machine mode being used. */
static int
@@ -34614,7 +34614,7 @@ arm_mve_load_store_insn_p (rtx_insn* insn,
are used.
If INSN is a MVE operation across lanes that is not predicated by
- VCTP_VPR_GENERATED it can not be validated by the use of its ouputs.
+ VCTP_VPR_GENERATED it can not be validated by the use of its outputs.
Any other INSN is safe to implicit predicate if we don't use its outputs
outside the loop. The instructions that use this INSN's outputs will be
@@ -34836,7 +34836,7 @@ arm_mve_check_reg_origin_is_num_elems (loop *loop, rtx
reg, rtx vctp_step,
if (DF_REG_DEF_COUNT (REGNO (reg)) > 2)
return false;
- /* Look for a single defition of REG going into the loop. The DEF_CHAIN will
+ /* Look for a single definition of REG going into the loop. The DEF_CHAIN
will
have at least two values, as this is a loop induction variable that is
defined outside the loop. */
for (df_ref def = DF_REG_DEF_CHAIN (REGNO (reg));
@@ -35130,7 +35130,7 @@ arm_mve_dlstp_check_dec_counter (loop *loop, rtx_insn*
vctp_insn,
}
/* If the decrements are the same, then the situation is simple: either they
are also the same reg, which is safe, or they are different registers, in
- which case makse sure that there is a only simple SET from one to the
+ which case make sure that there is a only simple SET from one to the
other inside the loop.*/
else if (decrementnum == arm_mve_get_vctp_lanes (vctp_insn))
{
@@ -35319,7 +35319,7 @@ arm_mve_loop_valid_for_dlstp (loop *loop)
/* Predict whether the given loop in gimple will be transformed in the RTL
doloop_optimize pass. It could be argued that turning large enough loops
- into low-overhead loops would not show a signficant performance boost.
+ into low-overhead loops would not show a significant performance boost.
However, in the case of tail predication we would still avoid using VPT/VPST
instructions inside the loop, and in either case using low-overhead loops
would not be detrimental, so we decided to not consider size, avoiding the
@@ -35390,7 +35390,7 @@ arm_loop_unroll_adjust (unsigned nunroll, struct loop
*loop)
return nunroll;
}
-/* Function to hadle emitting a VPT-unpredicated version of a VPT-predicated
+/* Function to handle emitting a VPT-unpredicated version of a VPT-predicated
insn to a sequence. */
static bool
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index c97d79bdad0..10786ec914d 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -893,7 +893,7 @@ extern const int arm_arch_cde_coproc_bits[];
/* Round X up to the nearest word. */
#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
-/* Convert fron bytes to ints. */
+/* Convert from bytes to ints. */
#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* The number of (integer) registers required to hold a quantity of type MODE.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 2a72dde3647..febff17df0b 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -314,7 +314,7 @@
; that the instruction does not use or alter the condition codes.
;
; NOCOND means that the instruction does not use or alter the condition
-; codes but can be converted into a conditionally exectuted instruction.
+; codes but can be converted into a conditionally executed instruction.
; Given that NOCOND is the default for most instructions if omitted,
; the attribute predicable must be set to yes as well.
@@ -1057,7 +1057,7 @@
(set_attr "type" "alus_imm")]
)
-;; We can handle more constants efficently if we can clobber either a scratch
+;; We can handle more constants efficiently if we can clobber either a scratch
;; or the other source operand. We deliberately leave this late as in
;; high register pressure situations it's not worth forcing any reloads.
(define_peephole2
@@ -11661,7 +11661,7 @@
)
;; Note - although unspec_volatile's USE all hard registers,
-;; USEs are ignored after relaod has completed. Thus we need
+;; USEs are ignored after reload has completed. Thus we need
;; to add an unspec of the link register to ensure that flow
;; does not think that it is unused by the sibcall branch that
;; will replace the standard function epilogue.
@@ -11690,7 +11690,7 @@
emit_move_insn (ra, operands[2]);
operands[2] = ra;
}
- /* This is a hack -- we may have crystalized the function type too
+ /* This is a hack -- we may have crystallized the function type too
early. */
cfun->machine->func_type = 0;
}"
diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
index 8e1d12af9af..d9ab0e1127b 100644
--- a/gcc/config/arm/constraints.md
+++ b/gcc/config/arm/constraints.md
@@ -133,7 +133,7 @@
(match_test "(ival & 0xfffff000) == 0"))))
(define_constraint "PJ"
- "@internal A constant that satisfies the Pj constrant if negated."
+ "@internal A constant that satisfies the Pj constraint if negated."
(and (match_code "const_int")
(and (match_test "TARGET_THUMB2")
(match_test "((-ival) & 0xfffff000) == 0"))))
diff --git a/gcc/config/arm/cortex-a17-neon.md
b/gcc/config/arm/cortex-a17-neon.md
index 0ad7aaf9cb9..d42f9fef816 100644
--- a/gcc/config/arm/cortex-a17-neon.md
+++ b/gcc/config/arm/cortex-a17-neon.md
@@ -403,7 +403,7 @@
(eq_attr "cortex_a17_neon_type" "neon_fp_recpe_rsqrte_q"))
"(ca17_asimd0+ca17_perm0)*2|(ca17_asimd1+ca17_perm1)*2")
-;; Miscelaneous Instructions.
+;; Miscellaneous Instructions.
(define_insn_reservation
"cortex_a17_neon_bitops" 4
diff --git a/gcc/config/arm/cortex-r4f.md b/gcc/config/arm/cortex-r4f.md
index 0ab69ffa553..61f01435836 100644
--- a/gcc/config/arm/cortex-r4f.md
+++ b/gcc/config/arm/cortex-r4f.md
@@ -23,7 +23,7 @@
;; registers are early registers. Thus base latencies are 1 more than
;; those listed in the TRM.
-;; We use the A, B abd C units from the integer core, plus two additional
+;; We use the A, B and C units from the integer core, plus two additional
;; units to enforce VFP dual issue constraints.
;; A B C V1 VMLA
diff --git a/gcc/config/arm/crypto.md b/gcc/config/arm/crypto.md
index b645b0512f0..c9a9c559c00 100644
--- a/gcc/config/arm/crypto.md
+++ b/gcc/config/arm/crypto.md
@@ -130,7 +130,7 @@
;; When AESE/AESMC fusion is enabled we really want to keep the two together
;; and enforce the register dependency without scheduling or register
-;; allocation messing up the order or introducing moves inbetween.
+;; allocation messing up the order or introducing moves in between.
;; Mash the two together during combine.
(define_insn "*aarch32_crypto_aese_fused"
@@ -169,7 +169,7 @@
;; When AESD/AESIMC fusion is enabled we really want to keep the two together
;; and enforce the register dependency without scheduling or register
-;; allocation messing up the order or introducing moves inbetween.
+;; allocation messing up the order or introducing moves in between.
;; Mash the two together during combine.
(define_insn "*aarch32_crypto_aesd_fused"
diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h
index fb5ad86a57d..c083e2e5987 100644
--- a/gcc/config/arm/elf.h
+++ b/gcc/config/arm/elf.h
@@ -93,7 +93,7 @@
Otherwise, the readonly data section is used. */
/* The choice of placement for jump tables is nuanced. For cores with
Harvard caches (pretty much all cases these days), there is a
- benefit of maintaing a separation between I- and D-cache candidates
+ benefit of maintaining a separation between I- and D-cache candidates
and that favors having jump tables in the RO data section. This
makes the dispatch sequence slightly longer as we need to load the
address of the jump table first, but we often save elsewhere as the
diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md
index 6036c7a4926..f7229c36cb5 100644
--- a/gcc/config/arm/fa726te.md
+++ b/gcc/config/arm/fa726te.md
@@ -140,7 +140,7 @@
;; Here we model the resource conflict between Load@E3-stage & Store@W-stage.
;; The 2nd LSU (lsu1) is to model the fact that if 2 loads are scheduled in the
;; same "bundle", and the 2nd load will introudce another ISSUE stall but is
-;; still ok to execute (and may be benefical sometimes).
+;; still ok to execute (and may be beneficial sometimes).
(define_insn_reservation "726te_load1_op" 3
(and (eq_attr "tune" "fa726te")
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 9390671b138..c8fd31b52c5 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -2110,7 +2110,7 @@
(define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")])
(define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")])
-;; String reprentations of operations on the sign of a number.
+;; String representations of operations on the sign of a number.
(define_code_attr absneg_str [(abs "abs") (neg "neg")])
;; Conversions.
@@ -2268,7 +2268,7 @@
(UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m")
(UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")])
-;; Some of the vrint instuctions are predicable.
+;; Some of the vrint instructions are predicable.
(define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no")
(UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no")
(UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")])
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 80690a99238..603bdc1ab82 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -964,7 +964,7 @@
;; 64-bit shifts
;; This pattern loads a 32-bit shift count into a 64-bit NEON register,
-;; leaving the upper half uninitalized. This is OK since the shift
+;; leaving the upper half uninitialized. This is OK since the shift
;; instruction only looks at the low 8 bits anyway. To avoid confusing
;; data flow analysis however, we pretend the full register is set
;; using an unspec.
diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index db0fab2e1f6..611d8b88502 100644
--- a/gcc/config/arm/thumb1.md
+++ b/gcc/config/arm/thumb1.md
@@ -35,7 +35,7 @@
;; or clobbering the flags. Instead, they have the attribute "conds"
;; with value "set" or "clob". However, this attribute is not used to
;; identify dependencies and therefore the scheduler might reorder
-;; these instruction. Currenly, this problem cannot happen because
+;; these instruction. Currently, this problem cannot happen because
;; there are no separate Thumb1 patterns for individual instruction
;; that consume flags (except conditional execution, which is treated
;; differently). In particular there is no Thumb1 armv6-m pattern for
@@ -1070,7 +1070,7 @@
;; A pattern to recognize a special situation and optimize for it.
-;; On the thumb, zero-extension from memory is preferrable to sign-extension
+;; On the thumb, zero-extension from memory is preferable to sign-extension
;; due to the available addressing modes. Hence, convert a signed comparison
;; with zero into an unsigned comparison with 127 if possible.
(define_expand "cbranchqi4"
diff --git a/gcc/config/arm/uclinuxfdpiceabi.h
b/gcc/config/arm/uclinuxfdpiceabi.h
index 76d5ae528ba..b4d7b3f168a 100644
--- a/gcc/config/arm/uclinuxfdpiceabi.h
+++ b/gcc/config/arm/uclinuxfdpiceabi.h
@@ -40,7 +40,7 @@
force -pie. */
/* -static is not supported, because we have to define the
dynamic-linker, as we have some relocations to resolve at load
- time. We do not generate an error in case the user explictly passes
+ time. We do not generate an error in case the user explicitly passes
the -dynamic-linker option to the linker. */
#undef SUBTARGET_EXTRA_LINK_SPEC
#define SUBTARGET_EXTRA_LINK_SPEC \
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index 458bcda6ec6..f8c895ffd54 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -1,4 +1,4 @@
-;; Unspec defintions.
+;; Unspec definitions.
;; Copyright (C) 2012-2026 Free Software Foundation, Inc.
;; Contributed by ARM Ltd.
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 87219700780..87e4ae6901d 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -134,7 +134,7 @@
;; Vector forms for the IEEE-754 fmax()/fmin() functions
;; Fixme: Should be enabled for MVE as well, but currently that uses an
-;; incompatible expasion.
+;; incompatible expansion.
(define_expand "<fmaxmin><mode>3"
[(set (match_operand:VF 0 "s_register_operand" "")
(unspec:VF [(match_operand:VF 1 "s_register_operand")
diff --git a/gcc/config/arm/vxworks.h b/gcc/config/arm/vxworks.h
index b1b3f3c0957..8bcf8766e8e 100644
--- a/gcc/config/arm/vxworks.h
+++ b/gcc/config/arm/vxworks.h
@@ -143,7 +143,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.
If not, see
8K is reserved in the stack to propagate exceptions in case of overflow. */
#define STACK_CHECK_PROTECT 8192
-/* Unless overridded by the target options, the default is little-endian. */
+/* Unless overridden by the target options, the default is little-endian. */
#define TARGET_ENDIAN_DEFAULT 0
/* The VxWorks environment on ARM is llvm based and we need to link
diff --git a/libgcc/config/arm/fp16.c b/libgcc/config/arm/fp16.c
index 2049121ad19..81df92809a6 100644
--- a/libgcc/config/arm/fp16.c
+++ b/libgcc/config/arm/fp16.c
@@ -152,7 +152,7 @@ __gnu_float2h_internal (const struct format* fmt,
before adding it to the calculated exponent.
2. When we were calculating rounding, we left the mantissa with the
number of bits of the source operand, it needs reduced to ten
- bits (+1 for the afforementioned leading 1) by shifting right by
+ bits (+1 for the aforementioned leading 1) by shifting right by
the number of bits in the source mantissa - 10.
3. To ensure the leading 1 in the mantissa is applied to the exponent
we need to add the mantissa rather than apply an arithmetic "or"
--
2.43.0
