;; All SVE predicate modes.
(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
@@ -1061,6 +1064,7 @@ (define_c_enum "unspec"
UNSPEC_F2CVTL ; Used in aarch64-sve2.md.
UNSPEC_F2CVTLT ; Used in aarch64-sve2.md.
UNSPEC_FADDP ; Used in aarch64-sve2.md.
+ UNSPEC_FCVT ; Used in aarch64-sve2.md.
UNSPEC_FCVTNB ; Used in aarch64-sve2.md.
UNSPEC_FCVTNT ; Used in aarch64-sve2.md.
UNSPEC_FMAXNMP ; Used in aarch64-sve2.md.
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-
asm/cvt_mf8_bf16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-
asm/cvt_mf8_bf16_x2.c
new file mode 100644
index 00000000000..bdda0fd36d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c
@@ -0,0 +1,56 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#pragma GCC target "+fp8+bf16"
+#include "test_sme2_acle.h"
+
+/*
+** cvt_z0_z0:
+** msr fpmr, x0
+** bfcvt z0\.b, {z0\.h - z1\.h}
+** ret
+*/
+TEST_X2_NARROW (cvt_z0_z0, svbfloat16x2_t, svmfloat8_t,
+ z0_res = svcvt_mf8_bf16_x2_fpm (z0, fpm0),
+ z0_res = svcvt_mf8_fpm (z0, fpm0))
+
+/*
+** cvt_z0_z6:
+** msr fpmr, x0
+** bfcvt z0\.b, {z6\.h - z7\.h}
+** ret
+*/
+TEST_X2_NARROW (cvt_z0_z6, svbfloat16x2_t, svmfloat8_t,
+ z0_res = svcvt_mf8_bf16_x2_fpm (z6, fpm0),
+ z0_res = svcvt_mf8_fpm (z6, fpm0))
+
+/*
+** cvt_z0_z29:
+** msr fpmr, x0
+** mov [^\n]+
+** mov [^\n]+
+** bfcvt z0\.b, [^\n]+
+** ret
+*/
+TEST_X2_NARROW (cvt_z0_z29, svbfloat16x2_t, svmfloat8_t,
+ z0_res = svcvt_mf8_bf16_x2_fpm (z29, fpm0),
+ z0_res = svcvt_mf8_fpm (z29, fpm0))
+
+/*
+** cvt_z5_z0:
+** msr fpmr, x0
+** bfcvt z5\.b, {z0\.h - z1\.h}
+** ret
+*/
+TEST_X2_NARROW (cvt_z5_z0, svbfloat16x2_t, svmfloat8_t,
+ z5 = svcvt_mf8_bf16_x2_fpm (z0, fpm0),
+ z5 = svcvt_mf8_fpm (z0, fpm0))
+
+/*
+** cvt_z22_z16:
+** msr fpmr, x0
+** bfcvt z22\.b, {z16\.h - z17\.h}
+** ret
+*/
+TEST_X2_NARROW (cvt_z22_z16, svbfloat16x2_t, svmfloat8_t,
+ z22 = svcvt_mf8_bf16_x2_fpm (z16, fpm0),
+ z22 = svcvt_mf8_fpm (z16, fpm0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-
asm/cvt_mf8_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-
asm/cvt_mf8_f16_x2.c
new file mode 100644
index 00000000000..93792e90945
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c
@@ -0,0 +1,56 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+fp8"
+
+/*
+** cvt_z0_z0:
+** msr fpmr, x0
+** fcvt z0\.b, {z0\.h - z1\.h}
+** ret
+*/
+TEST_X2_NARROW (cvt_z0_z0, svfloat16x2_t, svmfloat8_t,
+ z0_res = svcvt_mf8_f16_x2_fpm (z0, fpm0),
+ z0_res = svcvt_mf8_fpm (z0, fpm0))
+
+/*
+** cvt_z0_z6:
+** msr fpmr, x0
+** fcvt z0\.b, {z6\.h - z7\.h}
+** ret
+*/
+TEST_X2_NARROW (cvt_z0_z6, svfloat16x2_t, svmfloat8_t,
+ z0_res = svcvt_mf8_f16_x2_fpm (z6, fpm0),
+ z0_res = svcvt_mf8_fpm (z6, fpm0))
+
+/*
+** cvt_z0_z29:
+** msr fpmr, x0
+** mov [^\n]+
+** mov [^\n]+
+** fcvt z0\.b, {z0\.h - z1\.h}
+** ret
+*/
+TEST_X2_NARROW (cvt_z0_z29, svfloat16x2_t, svmfloat8_t,
+ z0_res = svcvt_mf8_f16_x2_fpm (z29, fpm0),
+ z0_res = svcvt_mf8_fpm (z29, fpm0))
+
+/*
+** cvt_z5_z0:
+** msr fpmr, x0
+** fcvt z5\.b, {z0\.h - z1\.h}
+** ret
+*/
+TEST_X2_NARROW (cvt_z5_z0, svfloat16x2_t, svmfloat8_t,
+ z5 = svcvt_mf8_f16_x2_fpm (z0, fpm0),
+ z5 = svcvt_mf8_fpm (z0, fpm0))
+
+/*
+** cvt_z22_z16:
+** msr fpmr, x0
+** fcvt z22\.b, {z16\.h - z17\.h}
+** ret
+*/
+TEST_X2_NARROW (cvt_z22_z16, svfloat16x2_t, svmfloat8_t,
+ z22 = svcvt_mf8_f16_x2_fpm (z16, fpm0),
+ z22 = svcvt_mf8_fpm (z16, fpm0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-
asm/cvt_mf8_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-
asm/cvt_mf8_f32_x4.c
new file mode 100644
index 00000000000..a9ee10de0df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c
@@ -0,0 +1,72 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+fp8"
+
+/*
+** cvt_z0_z0:
+** msr fpmr, x0
+** fcvt z0\.b, {z0\.s - z3\.s}
+** ret
+*/
+TEST_X4_NARROW (cvt_z0_z0, svfloat32x4_t, svmfloat8_t,
+ z0_res = svcvt_mf8_f32_x4_fpm (z0, fpm0),
+ z0_res = svcvt_mf8_fpm (z0, fpm0))
+
+/*
+** cvt_z0_z4:
+** msr fpmr, x0
+** fcvt z0\.b, {z4\.s - z7\.s}
+** ret
+*/
+TEST_X4_NARROW (cvt_z0_z4, svfloat32x4_t, svmfloat8_t,
+ z0_res = svcvt_mf8_f32_x4_fpm (z4, fpm0),
+ z0_res = svcvt_mf8_fpm (z4, fpm0))
+
+/*
+** cvt_z0_z21:
+** msr fpmr, x0
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** fcvt z0\.b, [^\n]+
+** ret
+*/
+TEST_X4_NARROW (cvt_z0_z21, svfloat32x4_t, svmfloat8_t,
+ z0_res = svcvt_mf8_f32_x4_fpm (z21, fpm0),
+ z0_res = svcvt_mf8_fpm (z21, fpm0))
+
+/*
+** cvt_z25_z26:
+** msr fpmr, x0
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** fcvt z25\.b, {z28\.s - z31\.s}
+** ret
+*/
+TEST_X4_NARROW (cvt_z25_z26, svfloat32x4_t, svmfloat8_t,
+ z25 = svcvt_mf8_f32_x4_fpm (z26, fpm0),
+ z25 = svcvt_mf8_fpm (z26, fpm0))
+
+/*
+** cvt_z25_z0:
+** msr fpmr, x0
+** fcvt z25\.b, {z0\.s - z3\.s}
+** ret
+*/
+TEST_X4_NARROW (cvt_z25_z0, svfloat32x4_t, svmfloat8_t,
+ z25 = svcvt_mf8_f32_x4_fpm (z0, fpm0),
+ z25 = svcvt_mf8_fpm (z0, fpm0))
+
+/*
+** cvt_z22_z16:
+** msr fpmr, x0
+** fcvt z22\.b, {z16\.s - z19\.s}
+** ret
+*/
+TEST_X4_NARROW (cvt_z22_z16, svfloat32x4_t, svmfloat8_t,
+ z22_res = svcvt_mf8_f32_x4_fpm (z16, fpm0),
+ z22_res = svcvt_mf8_fpm (z16, fpm0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-
asm/cvtn_mf8_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-
asm/cvtn_mf8_f32_x4.c
new file mode 100644
index 00000000000..2d0bd7eda0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c
@@ -0,0 +1,72 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+fp8"
+
+/*
+** cvtn_z0_z0:
+** msr fpmr, x0
+** fcvtn z0\.b, {z0\.s - z3\.s}
+** ret
+*/
+TEST_X4_NARROW (cvtn_z0_z0, svfloat32x4_t, svmfloat8_t,
+ z0_res = svcvtn_mf8_f32_x4_fpm (z0, fpm0),
+ z0_res = svcvtn_mf8_fpm (z0, fpm0))
+
+/*
+** cvtn_z0_z4:
+** msr fpmr, x0
+** fcvtn z0\.b, {z4\.s - z7\.s}
+** ret
+*/
+TEST_X4_NARROW (cvtn_z0_z4, svfloat32x4_t, svmfloat8_t,
+ z0_res = svcvtn_mf8_f32_x4_fpm (z4, fpm0),
+ z0_res = svcvtn_mf8_fpm (z4, fpm0))
+
+/*
+** cvtn_z0_z21:
+** msr fpmr, x0
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** fcvtn z0\.b, [^\n]+
+** ret
+*/
+TEST_X4_NARROW (cvtn_z0_z21, svfloat32x4_t, svmfloat8_t,
+ z0_res = svcvtn_mf8_f32_x4_fpm (z21, fpm0),
+ z0_res = svcvtn_mf8_fpm (z21, fpm0))
+
+/*
+** cvtn_z25_z26:
+** msr fpmr, x0
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** fcvtn z25\.b, {z28\.s - z31\.s}
+** ret
+*/
+TEST_X4_NARROW (cvtn_z25_z26, svfloat32x4_t, svmfloat8_t,
+ z25 = svcvtn_mf8_f32_x4_fpm (z26, fpm0),
+ z25 = svcvtn_mf8_fpm (z26, fpm0))
+
+/*
+** cvtn_z25_z0:
+** msr fpmr, x0
+** fcvtn z25\.b, {z0\.s - z3\.s}
+** ret
+*/
+TEST_X4_NARROW (cvtn_z25_z0, svfloat32x4_t, svmfloat8_t,
+ z25 = svcvtn_mf8_f32_x4_fpm (z0, fpm0),
+ z25 = svcvtn_mf8_fpm (z0, fpm0))
+
+/*
+** cvtn_z22_z16:
+** msr fpmr, x0
+** fcvtn z22\.b, {z16\.s - z19\.s}
+** ret
+*/
+TEST_X4_NARROW (cvtn_z22_z16, svfloat32x4_t, svmfloat8_t,
+ z22_res = svcvtn_mf8_f32_x4_fpm (z16, fpm0),
+ z22_res = svcvtn_mf8_fpm (z16, fpm0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h
index 7c156c4cf2a..8d4ed537c87 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h
@@ -733,6 +733,7 @@
#define TEST_X2_NARROW(NAME, TTYPE, ZTYPE, CODE1, CODE2) \
PROTO (NAME, void, ()) \
{ \
+ register fpm_t fpm0 __asm ("x0"); \
register TTYPE z0 __asm ("z0"); \
register ZTYPE z5 __asm ("z5"); \
register TTYPE z6 __asm ("z6"); \
@@ -749,6 +750,7 @@
#define TEST_X4_NARROW(NAME, TTYPE, ZTYPE, CODE1, CODE2) \
PROTO (NAME, void, ()) \
{ \
+ register fpm_t fpm0 __asm ("x0"); \
register TTYPE z0 __asm ("z0"); \
register TTYPE z4 __asm ("z4"); \
register TTYPE z16 __asm ("z16"); \
--
2.51.0
