On Fri, Jul 11, 2025 at 9:13 AM Li, Pan2 <pan2...@intel.com> wrote: > > Thanks Richard for comments. > > > Why is it important to constrain the widen-mult input to a > > fixed precision at all? > > I suppose widen-mult only occurs when the result exceed the max bits of gpr. > So, here I would like to make sure the precision is matching the bits of gpr. > > For rv32 with 32-bits gpr, 32 bits * 32 bits => 64 bits > > 15 │ _1 = (long long unsigned int) a_4(D); > 16 │ _2 = (long long unsigned int) b_5(D); > 17 │ _9 = (unsigned int) _1; > 18 │ _10 = (unsigned int) _2; > 19 │ x_6 = _9 w* _10; > > For rv64 with 64-bits gpr, 64 bits * 64 bits => 128 bits > > 15 │ _1 = (__int128 unsigned) a_4(D); > 16 │ _2 = (__int128 unsigned) b_5(D); > 17 │ _9 = (unsigned long) _1; > 18 │ _10 = (unsigned long) _2; > 19 │ x_6 = _9 w* _10; > > But if it is a widen-mul, it looks like that the ops of widen-mul should be > the max bits of gpr already. > Or it will be a normal mul, then looks we don't need to check that anymore, > am I understanding correct?
A widen-mul could also be a QImode x QImode -> HImode operation, or a QImode x QImode -> SImode operation. The only restriction is the result is at least twice as wide as the inputs. Richard. > > Pan > > -----Original Message----- > From: Richard Biener <richard.guent...@gmail.com> > Sent: Friday, July 11, 2025 2:23 PM > To: Li, Pan2 <pan2...@intel.com> > Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com; > jeffreya...@gmail.com; rdapp....@gmail.com; Chen, Ken <ken.c...@intel.com>; > Liu, Hongtao <hongtao....@intel.com> > Subject: Re: [PATCH v1 1/2] Match: Leverage BITS_PER_WORD for unsigned > SAT_MUL pattern > > On Fri, Jul 11, 2025 at 6:51 AM <pan2...@intel.com> wrote: > > > > From: Pan Li <pan2...@intel.com> > > > > The widen mul has different source type for differnt platform, > > like rv32 or rv64. For rv32, the source of widen mul is 32-bits > > while 64-bits in rv64. Thus, leverage HOST_WIDE_INT is not that > > correct and result in the pattern match failures in 32-bits system > > like rv32. > > > > Thus, leverage the BITS_PER_WORD instead for this pattern. > > > > gcc/ChangeLog: > > > > * match.pd: Leverage BITS_PER_WORD instead of HOST_WIDE_INT > > for widen mul precision check. > > > > Signed-off-by: Pan Li <pan2...@intel.com> > > --- > > gcc/match.pd | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > diff --git a/gcc/match.pd b/gcc/match.pd > > index 67b33eee5f7..7f31705b652 100644 > > --- a/gcc/match.pd > > +++ b/gcc/match.pd > > @@ -3605,11 +3605,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) > > unsigned widen_prec = TYPE_PRECISION (TREE_TYPE (@3)); > > unsigned cvt5_prec = TYPE_PRECISION (TREE_TYPE (@5)); > > unsigned cvt6_prec = TYPE_PRECISION (TREE_TYPE (@6)); > > - unsigned hw_int_prec = sizeof (HOST_WIDE_INT) * 8; > > wide_int c2 = wi::to_wide (@2); > > wide_int max = wi::mask (prec, false, widen_prec); > > bool c2_is_max_p = wi::eq_p (c2, max); > > - bool widen_mult_p = cvt5_prec == cvt6_prec && hw_int_prec == > > cvt5_prec; > > + bool widen_mult_p = cvt5_prec == cvt6_prec && BITS_PER_WORD == > > cvt5_prec; > > Why is it important to constrain the widen-mult input to a > fixed precision at all? > > > } > > (if (widen_prec > prec && c2_is_max_p && widen_mult_p))))) > > ) > > -- > > 2.43.0 > >
