Spencer Abson <spencer.ab...@arm.com> writes:
> diff --git a/gcc/config/aarch64/aarch64-sve.md
> b/gcc/config/aarch64/aarch64-sve.md
> index 399d147c9a5..1a705e153cb 100644
> --- a/gcc/config/aarch64/aarch64-sve.md
> +++ b/gcc/config/aarch64/aarch64-sve.md
> @@ -3762,13 +3762,28 @@
>
> ;; Unpredicated floating-point unary operations.
> (define_expand "<optab><mode>2"
> - [(set (match_operand:SVE_FULL_F 0 "register_operand")
> - (unspec:SVE_FULL_F
> + [(set (match_operand:SVE_F 0 "register_operand")
> + (unspec:SVE_F
> [(match_dup 2)
> - (const_int SVE_RELAXED_GP)
> - (match_operand:SVE_FULL_F 1 "register_operand")]
> + (match_dup 3)
> + (match_operand:SVE_F 1 "register_operand")]
> SVE_COND_FP_UNARY_OPTAB))]
> "TARGET_SVE"
> + {
> + operands[2] = aarch64_sve_fp_pred (<MODE>mode, &operands[3]);
> + }
> +)
> +
> +;; FABS and FNEG are non-trapping, we can always expand with their
> +;; natural PTRUE.
Here too, I'm not sure about calling this "natural". If we view VNx2SF
as a mode with 64-bit containers, governed by VNx2BI, then in a sense,
the .D ptrue is the natural ptrue, and would work for all cases
(trapping and non-trapping). The difficulty is that only the low bit
of each byte in a VNx2BI is significant and we try to reuse a single .B
ptrue as much as possible.
Maybe:
;; FABS and FNEG are non-trapping, so we can always expand with a <VPRED>
;; predicate. It doesn't matter whether the padding bits of a partial
;; vector mode are active or inactive.
Again, please push back if you have an alternative suggestion.
OK with that change, thanks.
Richard
