Spencer Abson <spencer.ab...@arm.com> writes: > This patch extends the expanders for unpredicated smax, smin, add, sub, > mul, min, and max, so that they support partial SVE FP modes. > > The relevant insn/split patterns have also been updated. > > gcc/ChangeLog: > > * config/aarch64/aarch64-sve.md (<optab><mode>3): Extend from > SVE_FULL_F to SVE_F, and use aarch64_sve_fp_pred. > (@aarch64_pred_<optab><mode>): Extend from SVE_FULL_F to SVE_F, > use aarch64_predicate_operand. (ADD/SUB/MUL/MAX/MIN). > * config/aarch64/aarch64-sve2.md: Likewise, for BF16 operations. > > gcc/testsuite/ChangeLog: > > * g++.target/aarch64/sve/unpacked_binary_bf16_1.C: New test. > * g++.target/aarch64/sve/unpacked_binary_bf16_2.C: Likewise. > * gcc.target/aarch64/sve/unpacked_builtin_fmax_1.c: Likewise. > * gcc.target/aarch64/sve/unpacked_builtin_fmax_2.c: Likewise. > * gcc.target/aarch64/sve/unpacked_builtin_fmin_1.c: Likewise. > * gcc.target/aarch64/sve/unpacked_builtin_fmin_2.c: Likewise. > * gcc.target/aarch64/sve/unpacked_fadd_1.c: Likewise. > * gcc.target/aarch64/sve/unpacked_fadd_2.c: Likewise. > * gcc.target/aarch64/sve/unpacked_fmaxnm_1.c: Likewise. > * gcc.target/aarch64/sve/unpacked_fmaxnm_2.c: Likewise. > * gcc.target/aarch64/sve/unpacked_fminnm_1.c: Likewise. > * gcc.target/aarch64/sve/unpacked_fminnm_2.c: Likewise. > * gcc.target/aarch64/sve/unpacked_fmul_1.c: Likewise. > * gcc.target/aarch64/sve/unpacked_fmul_2.c: Likewise. > * gcc.target/aarch64/sve/unpacked_fsubr_1.c: Likewise. > * gcc.target/aarch64/sve/unpacked_fsubr_2.c: Likewise.
OK, thanks. > --- > gcc/config/aarch64/aarch64-sve.md | 70 +++++++++---------- > gcc/config/aarch64/aarch64-sve2.md | 10 +-- > .../aarch64/sve/unpacked_binary_bf16_1.C | 35 ++++++++++ > .../aarch64/sve/unpacked_binary_bf16_2.C | 15 ++++ > .../aarch64/sve/unpacked_builtin_fmax_1.c | 40 +++++++++++ > .../aarch64/sve/unpacked_builtin_fmax_2.c | 16 +++++ > .../aarch64/sve/unpacked_builtin_fmin_1.c | 40 +++++++++++ > .../aarch64/sve/unpacked_builtin_fmin_2.c | 16 +++++ > .../gcc.target/aarch64/sve/unpacked_fadd_1.c | 48 +++++++++++++ > .../gcc.target/aarch64/sve/unpacked_fadd_2.c | 22 ++++++ > .../aarch64/sve/unpacked_fmaxnm_1.c | 41 +++++++++++ > .../aarch64/sve/unpacked_fmaxnm_2.c | 16 +++++ > .../aarch64/sve/unpacked_fminnm_1.c | 42 +++++++++++ > .../aarch64/sve/unpacked_fminnm_2.c | 16 +++++ > .../gcc.target/aarch64/sve/unpacked_fmul_1.c | 39 +++++++++++ > .../gcc.target/aarch64/sve/unpacked_fmul_2.c | 14 ++++ > .../gcc.target/aarch64/sve/unpacked_fsubr_1.c | 42 +++++++++++ > .../gcc.target/aarch64/sve/unpacked_fsubr_2.c | 16 +++++ > 18 files changed, 498 insertions(+), 40 deletions(-) > create mode 100644 > gcc/testsuite/g++.target/aarch64/sve/unpacked_binary_bf16_1.C > create mode 100644 > gcc/testsuite/g++.target/aarch64/sve/unpacked_binary_bf16_2.C > create mode 100644 > gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_1.c > create mode 100644 > gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_2.c > create mode 100644 > gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_1.c > create mode 100644 > gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_2.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_1.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_2.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_1.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_2.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_1.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_2.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_1.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_2.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_1.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_2.c > > diff --git a/gcc/config/aarch64/aarch64-sve.md > b/gcc/config/aarch64/aarch64-sve.md > index 76de511420f..cdad900d9cf 100644 > --- a/gcc/config/aarch64/aarch64-sve.md > +++ b/gcc/config/aarch64/aarch64-sve.md > @@ -5473,27 +5473,27 @@ > ;; Split a predicated instruction whose predicate is unused into an > ;; unpredicated instruction. > (define_split > - [(set (match_operand:SVE_FULL_F_B16B16 0 "register_operand") > - (unspec:SVE_FULL_F_B16B16 > + [(set (match_operand:SVE_F_B16B16 0 "register_operand") > + (unspec:SVE_F_B16B16 > [(match_operand:<VPRED> 1 "register_operand") > (match_operand:SI 4 "aarch64_sve_gp_strictness") > - (match_operand:SVE_FULL_F_B16B16 2 "register_operand") > - (match_operand:SVE_FULL_F_B16B16 3 "register_operand")] > + (match_operand:SVE_F_B16B16 2 "register_operand") > + (match_operand:SVE_F_B16B16 3 "register_operand")] > <SVE_COND_FP>))] > "TARGET_SVE > && reload_completed > && INTVAL (operands[4]) == SVE_RELAXED_GP" > [(set (match_dup 0) > - (SVE_UNPRED_FP_BINARY:SVE_FULL_F_B16B16 (match_dup 2) (match_dup 3)))] > + (SVE_UNPRED_FP_BINARY:SVE_F_B16B16 (match_dup 2) (match_dup 3)))] > ) Reading this back, I notice that I forgot to move the SVE_RELAXED_GP into the pattern when separating the define_split from the original define_insn_and_split. I'll do that as a follow-up. Richard
