This patch extends the compare/and splitting patterns for FP comparisons
from SVE_FULL_F to SVE_F.
gcc/ChangeLog:
* config/aarch64/aarch64-sve.md (*fcm<cmp_op><mode>_and_combine):
Extend to SVE_F.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/unpacked_fcm_1.c: Allow other tests
to define TEST_FCM (new ifdef guard).
* gcc.target/aarch64/sve/unpacked_fcm_and_1.c: New test.
---
gcc/config/aarch64/aarch64-sve.md | 8 ++++----
.../gcc.target/aarch64/sve/unpacked_fcm_1.c | 2 ++
.../aarch64/sve/unpacked_fcm_and_1.c | 18 ++++++++++++++++++
3 files changed, 24 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_and_1.c
diff --git a/gcc/config/aarch64/aarch64-sve.md
b/gcc/config/aarch64/aarch64-sve.md
index 6c5129bc0c6..399d147c9a5 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -8653,8 +8653,8 @@
(unspec:<VPRED>
[(match_operand:<VPRED> 1)
(const_int SVE_KNOWN_PTRUE)
- (match_operand:SVE_FULL_F 2 "register_operand" "w, w")
- (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "Dz, w")]
+ (match_operand:SVE_F 2 "register_operand" "w, w")
+ (match_operand:SVE_F 3 "aarch64_simd_reg_or_zero" "Dz, w")]
SVE_COND_FP_CMP_I0)
(match_operand:<VPRED> 4 "register_operand" "Upl, Upl")))]
"TARGET_SVE"
@@ -8676,8 +8676,8 @@
(unspec:<VPRED>
[(match_operand:<VPRED> 1)
(const_int SVE_KNOWN_PTRUE)
- (match_operand:SVE_FULL_F 2 "register_operand" "w")
- (match_operand:SVE_FULL_F 3 "register_operand" "w")]
+ (match_operand:SVE_F 2 "register_operand" "w")
+ (match_operand:SVE_F 3 "register_operand" "w")]
UNSPEC_COND_FCMUO)
(match_operand:<VPRED> 4 "register_operand" "Upl")))]
"TARGET_SVE"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_1.c
index 7e39b79991b..bc02763df0b 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_1.c
@@ -20,6 +20,7 @@
#define b_i b[i]
+#ifndef TEST_FCM
#define TEST_FCM(TYPE0, TYPE1, CMP, RHS, COUNT) \
void \
f_##TYPE0##_##TYPE1##_##CMP##_##RHS (TYPE0 *__restrict out, \
@@ -29,6 +30,7 @@
for (unsigned int i = 0; i < COUNT; i++) \
out[i] = CMP (a[i], RHS) ? 3 : out[i]; \
}
+#endif
#define TEST_CC_REG(CMP) \
TEST_FCM (uint64_t, float, CMP, b_i, 32) \
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_and_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_and_1.c
new file mode 100644
index 00000000000..2b88cc14a98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fcm_and_1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=2048
-fno-trapping-math" } */
+
+#define TEST_FCM(TYPE0, TYPE1, CMP, RHS, COUNT) \
+ void \
+ f_##TYPE0##_##TYPE1##_##CMP##_##RHS (TYPE0 *__restrict out, \
+ TYPE0 *__restrict p, \
+ TYPE1 *__restrict a, \
+ TYPE1 *__restrict b) \
+ { \
+ for (unsigned int i = 0; i < COUNT; i++) \
+ if (p[i] && CMP (a[i], RHS)) \
+ out[i] = 3; \
+ }
+
+#include "unpacked_fcm_1.c"
+
+/* { dg-final { scan-assembler-not {\tand\t} } } */
--
2.34.1
