From: Pan Li <pan2...@intel.com> Some existing avg_floor test need updated due to change to leverage vaadd.vv directly.
gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/avg-4.c: Update asm check to vaadd. * gcc.target/riscv/rvv/autovec/vls/avg-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/avg-6.c: Ditto. * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c: Ditto. Signed-off-by: Pan Li <pan2...@intel.com> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c | 6 ++---- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c | 6 ++---- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c | 6 ++---- .../gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c | 2 +- 5 files changed, 8 insertions(+), 14 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c index 8d106aaeed0..986a0ff21cf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c @@ -25,11 +25,9 @@ DEF_AVG_CEIL (uint8_t, uint16_t, 512) DEF_AVG_CEIL (uint8_t, uint16_t, 1024) DEF_AVG_CEIL (uint8_t, uint16_t, 2048) -/* { dg-final { scan-assembler-times {vwadd\.vv} 10 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 10 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 10 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 20 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 10 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 10 } } */ -/* { dg-final { scan-assembler-times {vadd\.vi} 10 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c index 981abd51588..c450f80291a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c @@ -23,11 +23,9 @@ DEF_AVG_CEIL (uint16_t, uint32_t, 256) DEF_AVG_CEIL (uint16_t, uint32_t, 512) DEF_AVG_CEIL (uint16_t, uint32_t, 1024) -/* { dg-final { scan-assembler-times {vwadd\.vv} 9 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 9 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 9 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 18 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 9 } } */ -/* { dg-final { scan-assembler-times {vadd\.vi} 9 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 9 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c index bfe4ba3c4bd..3473e193a5c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c @@ -21,11 +21,9 @@ DEF_AVG_CEIL (uint16_t, uint32_t, 128) DEF_AVG_CEIL (uint16_t, uint32_t, 256) DEF_AVG_CEIL (uint16_t, uint32_t, 512) -/* { dg-final { scan-assembler-times {vwadd\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 8 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 8 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 16 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {vadd\.vi} 8 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 8 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c index b7246a38dba..a5224e78d94 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c @@ -5,4 +5,4 @@ /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 6 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 6 } } */ -/* { dg-final { scan-assembler-times {vaadd\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c index 3ffe0ef39ee..32446ae3c23 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c @@ -5,4 +5,4 @@ /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 6 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 6 } } */ -/* { dg-final { scan-assembler-times {vaadd\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 6 } } */ -- 2.43.0