Remove most of the remaining code for iWMMXT support, except for the register allocation table entries.
gcc/ChangeLog: * config/arm/arm-cpus.in (feature iwmmxt, feature iwmmxt2): Delete. * config/arm/arm-protos.h (arm_output_iwmmxt_shift_immediate): Delete. (arm_output_iwmmxt_tinsr): Delete. (arm_arch_iwmmxt): Delete. (arm_arch_iwmmxt2): Delete. * config/arm/arm.h (TARGET_IWMMXT): Delete. (TARGET_IWMMXT2): Delete. (TARGET_REALLY_IWMMXT): Delete. (TARGET_REALLY_IWMMXT2): Delete. (VALID_IWMMXT_REG_MODE): Delete. (ARM_HAVE_V8QI_ARITH): Remove iWMMXT. (ARM_HAVE_V4HI_ARITH): Likewise. (ARM_HAVE_V2SI_ARITH): Likewise. (ARM_HAVE_V8QI_LDST): Likewise. (ARM_HAVE_V4HI_LDST): Likewise. (ARM_HAVE_V2SI_LDST): Likewise. (SECONDARY_OUTPUT_RELOAD_CLASS): Remove iWMMXT cases. (SECONDARY_INPUT_RELOAD_CLASS): Likewise. * config/arm/arm.cc (arm_arch_iwmmxt): Delete. (arm_arch_iwmmxt2): Delete. (arm_option_reconfigure_globals): Don't initialize them. (arm_register_move_cost): Remove costs for iwmmxt. (struct minipool_node): Update comment. (output_move_double): Likewise (output_return_instruction): Likewise. (arm_print_operand, cases 'U' and 'w'): Report an error if used. (arm_regno_class): Remove iWMMXT cases. (arm_debugger_regno): Remove iWMMXT cases. (arm_output_iwmmxt_shift_immediate): Delete. (arm_output_iwmmxt_tinsr): Delete. --- gcc/config/arm/arm-cpus.in | 6 -- gcc/config/arm/arm-protos.h | 8 -- gcc/config/arm/arm.cc | 174 ++---------------------------------- gcc/config/arm/arm.h | 69 +++++--------- 4 files changed, 32 insertions(+), 225 deletions(-) diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index b34c441ec76..7f5a8c670b6 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -102,12 +102,6 @@ define feature armv8 # ARMv8 CRC32 instructions. define feature crc32 -# XScale v2 (Wireless MMX). -define feature iwmmxt - -# XScale Wireless MMX2. -define feature iwmmxt2 - # Architecture rel 8.1. define feature armv8_1 diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 254c7310794..ff7e7658f91 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -190,8 +190,6 @@ extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool); extern void arm_set_return_address (rtx, rtx); extern int arm_eliminable_register (rtx); extern const char *arm_output_shift(rtx *, int); -extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool); -extern const char *arm_output_iwmmxt_tinsr (rtx *); extern unsigned int arm_sync_loop_insns (rtx , rtx *); extern int arm_attr_length_push_multi(rtx, rtx); extern int arm_attr_length_pop_multi(rtx *, bool, bool); @@ -475,12 +473,6 @@ extern int arm_ld_sched; /* Nonzero if this chip is a StrongARM. */ extern int arm_tune_strongarm; -/* Nonzero if this chip supports Intel Wireless MMX technology. */ -extern int arm_arch_iwmmxt; - -/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ -extern int arm_arch_iwmmxt2; - /* Nonzero if this chip is an XScale. */ extern int arm_arch_xscale; diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 11fd6dfb3ed..4d7c42bd5b8 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -948,12 +948,6 @@ int arm_ld_sched = 0; /* Nonzero if this chip is a StrongARM. */ int arm_tune_strongarm = 0; -/* Nonzero if this chip supports Intel Wireless MMX technology. */ -int arm_arch_iwmmxt = 0; - -/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ -int arm_arch_iwmmxt2 = 0; - /* Nonzero if this chip is an XScale. */ int arm_arch_xscale = 0; @@ -3919,8 +3913,6 @@ arm_option_reconfigure_globals (void) arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2); arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale); - arm_arch_iwmmxt = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt); - arm_arch_iwmmxt2 = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt2); arm_arch_thumb_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_tdiv); arm_arch_arm_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_adiv); arm_arch_crc = bitmap_bit_p (arm_active_target.isa, isa_bit_crc32); @@ -12378,11 +12370,6 @@ arm_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, if ((IS_VFP_CLASS (from) && !IS_VFP_CLASS (to)) || (!IS_VFP_CLASS (from) && IS_VFP_CLASS (to))) return 15; - else if ((from == IWMMXT_REGS && to != IWMMXT_REGS) - || (from != IWMMXT_REGS && to == IWMMXT_REGS)) - return 4; - else if (from == IWMMXT_GR_REGS || to == IWMMXT_GR_REGS) - return 20; else return 2; } @@ -17496,8 +17483,7 @@ struct minipool_node rtx value; /* The mode of value. */ machine_mode mode; - /* The size of the value. With iWMMXt enabled - sizes > 4 also imply an alignment of 8-bytes. */ + /* The size of the value. */ int fix_size; }; @@ -20160,9 +20146,7 @@ output_move_double (rtx *operands, bool emit, int *count) } else { - /* Use a single insn if we can. - FIXME: IWMMXT allows offsets larger than ldrd can - handle, fix these up with a pair of ldr. */ + /* Use a single insn if we can. */ if (can_ldrd && (TARGET_THUMB2 || !CONST_INT_P (otherops[2]) @@ -20187,9 +20171,7 @@ output_move_double (rtx *operands, bool emit, int *count) } else { - /* Use a single insn if we can. - FIXME: IWMMXT allows offsets larger than ldrd can handle, - fix these up with a pair of ldr. */ + /* Use a single insn if we can. */ if (can_ldrd && (TARGET_THUMB2 || !CONST_INT_P (otherops[2]) @@ -20427,8 +20409,6 @@ output_move_double (rtx *operands, bool emit, int *count) otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0); otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1); - /* IWMMXT allows offsets larger than strd can handle, - fix these up with a pair of str. */ if (!TARGET_THUMB2 && CONST_INT_P (otherops[2]) && (INTVAL(otherops[2]) <= -256 @@ -21572,12 +21552,10 @@ output_return_instruction (rtx operand, bool really_return, bool reverse, if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) { - /* There are three possible reasons for the IP register - being saved. 1) a stack frame was created, in which case - IP contains the old stack pointer, or 2) an ISR routine - corrupted it, or 3) it was saved to align the stack on - iWMMXt. In case 1, restore IP into SP, otherwise just - restore IP. */ + /* There are two possible reasons for the IP register being saved. + 1) a stack frame was created, in which case IP contains the old + stack pointer, or 2) an ISR routine corrupted it. In case 1, + restore IP into SP, otherwise just restore IP. */ if (frame_pointer_needed) { live_regs_mask &= ~ (1 << IP_REGNUM); @@ -24417,42 +24395,9 @@ arm_print_operand (FILE *stream, rtx x, int code) return; case 'U': - if (!REG_P (x) - || REGNO (x) < FIRST_IWMMXT_GR_REGNUM - || REGNO (x) > LAST_IWMMXT_GR_REGNUM) - /* Bad value for wCG register number. */ - { - output_operand_lossage ("invalid operand for code '%c'", code); - return; - } - - else - fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); - return; - - /* Print an iWMMXt control register name. */ case 'w': - if (!CONST_INT_P (x) - || INTVAL (x) < 0 - || INTVAL (x) >= 16) - /* Bad value for wC register number. */ - { - output_operand_lossage ("invalid operand for code '%c'", code); - return; - } - - else - { - static const char * wc_reg_names [16] = - { - "wCID", "wCon", "wCSSF", "wCASF", - "wC4", "wC5", "wC6", "wC7", - "wCGR0", "wCGR1", "wCGR2", "wCGR3", - "wC12", "wC13", "wC14", "wC15" - }; - - fputs (wc_reg_names [INTVAL (x)], stream); - } + /* Former iWMMXT support, removed after GCC-15. */ + output_operand_lossage ("obsolete iWMMXT format code '%c'", code); return; /* Print the high single-precision register of a VFP double-precision @@ -25892,12 +25837,6 @@ arm_regno_class (int regno) return VFP_HI_REGS; } - if (IS_IWMMXT_REGNUM (regno)) - return IWMMXT_REGS; - - if (IS_IWMMXT_GR_REGNUM (regno)) - return IWMMXT_GR_REGS; - return NO_REGS; } @@ -29840,12 +29779,6 @@ arm_debugger_regno (unsigned int regno) return 256 + (regno - FIRST_VFP_REGNUM) / 2; } - if (IS_IWMMXT_GR_REGNUM (regno)) - return 104 + regno - FIRST_IWMMXT_GR_REGNUM; - - if (IS_IWMMXT_REGNUM (regno)) - return 112 + regno - FIRST_IWMMXT_REGNUM; - if (IS_PAC_REGNUM (regno)) return DWARF_PAC_REGNUM; @@ -30432,95 +30365,6 @@ arm_output_shift(rtx * operands, int set_flags) return ""; } -/* Output assembly for a WMMX immediate shift instruction. */ -const char * -arm_output_iwmmxt_shift_immediate (const char *insn_name, rtx *operands, bool wror_or_wsra) -{ - int shift = INTVAL (operands[2]); - char templ[50]; - machine_mode opmode = GET_MODE (operands[0]); - - gcc_assert (shift >= 0); - - /* If the shift value in the register versions is > 63 (for D qualifier), - 31 (for W qualifier) or 15 (for H qualifier). */ - if (((opmode == V4HImode) && (shift > 15)) - || ((opmode == V2SImode) && (shift > 31)) - || ((opmode == DImode) && (shift > 63))) - { - if (wror_or_wsra) - { - sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, 32); - output_asm_insn (templ, operands); - if (opmode == DImode) - { - sprintf (templ, "%s\t%%0, %%0, #%d", insn_name, 32); - output_asm_insn (templ, operands); - } - } - else - { - /* The destination register will contain all zeros. */ - sprintf (templ, "wzero\t%%0"); - output_asm_insn (templ, operands); - } - return ""; - } - - if ((opmode == DImode) && (shift > 32)) - { - sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, 32); - output_asm_insn (templ, operands); - sprintf (templ, "%s\t%%0, %%0, #%d", insn_name, shift - 32); - output_asm_insn (templ, operands); - } - else - { - sprintf (templ, "%s\t%%0, %%1, #%d", insn_name, shift); - output_asm_insn (templ, operands); - } - return ""; -} - -/* Output assembly for a WMMX tinsr instruction. */ -const char * -arm_output_iwmmxt_tinsr (rtx *operands) -{ - int mask = INTVAL (operands[3]); - int i; - char templ[50]; - int units = mode_nunits[GET_MODE (operands[0])]; - gcc_assert ((mask & (mask - 1)) == 0); - for (i = 0; i < units; ++i) - { - if ((mask & 0x01) == 1) - { - break; - } - mask >>= 1; - } - gcc_assert (i < units); - { - switch (GET_MODE (operands[0])) - { - case E_V8QImode: - sprintf (templ, "tinsrb%%?\t%%0, %%2, #%d", i); - break; - case E_V4HImode: - sprintf (templ, "tinsrh%%?\t%%0, %%2, #%d", i); - break; - case E_V2SImode: - sprintf (templ, "tinsrw%%?\t%%0, %%2, #%d", i); - break; - default: - gcc_unreachable (); - break; - } - output_asm_insn (templ, operands); - } - return ""; -} - /* Output an arm casesi dispatch sequence. Used by arm_casesi_internal insn. Responsible for the handling of switch statements in arm. */ const char * diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 3f6fb0378ea..1990a276781 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -137,12 +137,6 @@ emission of floating point pcs attributes. */ #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) /* Use hardware floating point calling convention. */ #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) -#define TARGET_IWMMXT (arm_arch_iwmmxt) -#define TARGET_IWMMXT2 (arm_arch_iwmmxt2) -#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \ - && !TARGET_GENERAL_REGS_ONLY) -#define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \ - && !TARGET_GENERAL_REGS_ONLY) #define TARGET_ARM (! TARGET_THUMB) #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ #define TARGET_BACKTRACE (crtl->is_leaf \ @@ -525,12 +519,6 @@ extern int arm_ld_sched; /* Nonzero if this chip is a StrongARM. */ extern int arm_tune_strongarm; -/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ -extern int arm_arch_iwmmxt; - -/* Nonzero if this chip supports Intel Wireless MMX2 technology. */ -extern int arm_arch_iwmmxt2; - /* Nonzero if this chip is an XScale. */ extern int arm_arch_xscale; @@ -1085,9 +1073,6 @@ extern const int arm_arch_cde_coproc_bits[]; #define SUBTARGET_FRAME_POINTER_REQUIRED 0 #endif -#define VALID_IWMMXT_REG_MODE(MODE) \ - (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) - /* Modes valid for Neon D registers. */ #define VALID_NEON_DREG_MODE(MODE) \ ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ @@ -1167,9 +1152,9 @@ extern const int arm_arch_cde_coproc_bits[]; /* The conditions under which vector modes are supported for general arithmetic by any vector extension. */ -#define ARM_HAVE_V8QI_ARITH (ARM_HAVE_NEON_V8QI_ARITH || TARGET_REALLY_IWMMXT) -#define ARM_HAVE_V4HI_ARITH (ARM_HAVE_NEON_V4HI_ARITH || TARGET_REALLY_IWMMXT) -#define ARM_HAVE_V2SI_ARITH (ARM_HAVE_NEON_V2SI_ARITH || TARGET_REALLY_IWMMXT) +#define ARM_HAVE_V8QI_ARITH (ARM_HAVE_NEON_V8QI_ARITH) +#define ARM_HAVE_V4HI_ARITH (ARM_HAVE_NEON_V4HI_ARITH) +#define ARM_HAVE_V2SI_ARITH (ARM_HAVE_NEON_V2SI_ARITH) #define ARM_HAVE_V16QI_ARITH (ARM_HAVE_NEON_V16QI_ARITH || TARGET_HAVE_MVE) #define ARM_HAVE_V8HI_ARITH (ARM_HAVE_NEON_V8HI_ARITH || TARGET_HAVE_MVE) @@ -1203,9 +1188,9 @@ extern const int arm_arch_cde_coproc_bits[]; /* The conditions under which vector modes are supported by load/store instructions by any vector extension. */ -#define ARM_HAVE_V8QI_LDST (ARM_HAVE_NEON_V8QI_LDST || TARGET_REALLY_IWMMXT) -#define ARM_HAVE_V4HI_LDST (ARM_HAVE_NEON_V4HI_LDST || TARGET_REALLY_IWMMXT) -#define ARM_HAVE_V2SI_LDST (ARM_HAVE_NEON_V2SI_LDST || TARGET_REALLY_IWMMXT) +#define ARM_HAVE_V8QI_LDST (ARM_HAVE_NEON_V8QI_LDST) +#define ARM_HAVE_V4HI_LDST (ARM_HAVE_NEON_V4HI_LDST) +#define ARM_HAVE_V2SI_LDST (ARM_HAVE_NEON_V2SI_LDST) #define ARM_HAVE_V16QI_LDST (ARM_HAVE_NEON_V16QI_LDST || TARGET_HAVE_MVE) #define ARM_HAVE_V8HI_LDST (ARM_HAVE_NEON_V8HI_LDST || TARGET_HAVE_MVE) @@ -1460,41 +1445,33 @@ extern const char *fp_sysreg_names[NB_FP_SYSREGS]; or out of a register in CLASS in MODE. If it can be done directly, NO_REGS is returned. */ #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ - /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ + /* Restrict which direct reloads are allowed for VFP regs. */ \ ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ ? coproc_secondary_reload_class (MODE, X, FALSE) \ - : ((TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ - ? coproc_secondary_reload_class (MODE, X, TRUE) \ - : (TARGET_32BIT \ - ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ - ? GENERAL_REGS \ - : NO_REGS) \ - : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)))) + : (TARGET_32BIT \ + ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ + ? GENERAL_REGS \ + : NO_REGS) \ + : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))) /* If we need to load shorts byte-at-a-time, then we need a scratch. */ #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ - /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ + /* Restrict which direct reloads are allowed for VFP regs. */ \ ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ ? coproc_secondary_reload_class (MODE, X, FALSE) \ - : ((TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ - ? coproc_secondary_reload_class (MODE, X, TRUE) \ - : (TARGET_32BIT \ - ? ((((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ - && CONSTANT_P (X)) \ - ? GENERAL_REGS \ - : (((MODE) == HImode \ - && ! arm_arch4 \ - && (MEM_P (X) \ - || ((REG_P (X) || GET_CODE (X) == SUBREG) \ - && true_regnum (X) == -1))) \ - ? GENERAL_REGS \ - : NO_REGS)) \ - : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))) + : (TARGET_32BIT \ + ? (((MODE) == HImode \ + && ! arm_arch4 \ + && (MEM_P (X) \ + || ((REG_P (X) || GET_CODE (X) == SUBREG) \ + && true_regnum (X) == -1))) \ + ? GENERAL_REGS \ + : NO_REGS) \ + : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. - ARM regs are UNITS_PER_WORD bits. - FIXME: Is this true for iWMMX? */ + ARM regs are UNITS_PER_WORD bits. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ (CLASS == VPR_REG) \ ? CEIL (GET_MODE_SIZE (MODE), 2) \ -- 2.43.0