This patch deletes the patterns relating to iwmmxt and iwmmxt2 and
updates the relevant dependencies.
gcc/ChangeLog:
* config/arm/arm.md: Don't include iwmmxt.md.
* config/arm/t-arm (MD_INCLUDES): Remove iwmmxt*.md.
* config/arm/iwmmxt.md: Removed.
* config/arm/iwmmxt2.md: Removed.
* config/arm/unspecs.md: Remove comment referring to
iwmmxt2.md.
* config/arm/unspecs.md (enum unspec): Remove iWMMXt unspec
values.
(enum unspecv): Likewise.
* config/arm/predicates.md (imm_or_reg_operand): Delete.
---
gcc/config/arm/arm.md | 2 -
gcc/config/arm/iwmmxt.md | 1766 ----------------------------------
gcc/config/arm/iwmmxt2.md | 903 -----------------
gcc/config/arm/predicates.md | 8 +-
gcc/config/arm/t-arm | 2 -
gcc/config/arm/unspecs.md | 29 -
6 files changed, 1 insertion(+), 2709 deletions(-)
delete mode 100644 gcc/config/arm/iwmmxt.md
delete mode 100644 gcc/config/arm/iwmmxt2.md
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 597ef6725bb..af0564c36a9 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -13125,8 +13125,6 @@ (define_insn "bti_nop"
;; Vector bits common to IWMMXT, Neon and MVE
(include "vec-common.md")
-;; Load the Intel Wireless Multimedia Extension patterns
-(include "iwmmxt.md")
;; Load the VFP co-processor patterns
(include "vfp.md")
;; Thumb-1 patterns
diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md
deleted file mode 100644
index 0aa5dcd6709..00000000000
--- a/gcc/config/arm/iwmmxt.md
+++ /dev/null
@@ -1,1766 +0,0 @@
-;; Patterns for the Intel Wireless MMX technology architecture.
-;; Copyright (C) 2003-2025 Free Software Foundation, Inc.
-;; Contributed by Red Hat.
-
-;; This file is part of GCC.
-
-;; GCC is free software; you can redistribute it and/or modify it under
-;; the terms of the GNU General Public License as published by the Free
-;; Software Foundation; either version 3, or (at your option) any later
-;; version.
-
-;; GCC is distributed in the hope that it will be useful, but WITHOUT
-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
-;; License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING3. If not see
-;; <http://www.gnu.org/licenses/>.
-
-;; Register numbers. Need to sync with FIRST_IWMMXT_GR_REGNUM in arm.h
-(define_constants
- [(WCGR0 96)
- (WCGR1 97)
- (WCGR2 98)
- (WCGR3 99)
- ]
-)
-
-(define_insn "tbcstv8qi"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (vec_duplicate:V8QI (match_operand:QI 1 "s_register_operand" "r")))]
- "TARGET_REALLY_IWMMXT"
- "tbcstb%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tbcst")]
-)
-
-(define_insn "tbcstv4hi"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_duplicate:V4HI (match_operand:HI 1 "s_register_operand" "r")))]
- "TARGET_REALLY_IWMMXT"
- "tbcsth%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tbcst")]
-)
-
-(define_insn "tbcstv2si"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_duplicate:V2SI (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_REALLY_IWMMXT"
- "tbcstw%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tbcst")]
-)
-
-(define_insn "iwmmxt_iordi3"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (ior:DI (match_operand:DI 1 "register_operand" "%y")
- (match_operand:DI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wor%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "length" "4")
- (set_attr "type" "wmmx_wor")]
-)
-
-(define_insn "iwmmxt_xordi3"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (xor:DI (match_operand:DI 1 "register_operand" "%y")
- (match_operand:DI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wxor%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "length" "4")
- (set_attr "type" "wmmx_wxor")]
-)
-
-(define_insn "iwmmxt_anddi3"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (and:DI (match_operand:DI 1 "register_operand" "%y")
- (match_operand:DI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wand%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "length" "4")
- (set_attr "type" "wmmx_wand")]
-)
-
-(define_insn "iwmmxt_nanddi3"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (and:DI (match_operand:DI 1 "register_operand" "y")
- (not:DI (match_operand:DI 2 "register_operand" "y"))))]
- "TARGET_REALLY_IWMMXT"
- "wandn%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wandn")]
-)
-
-(define_insn "*iwmmxt_arm_movdi"
- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m,y,y,r,
y,Uy,*w, r,*w,*w, *Uv")
- (match_operand:DI 1 "di_operand"
"rDa,Db,Dc,mi,r,y,r,y,Uy,y, r,*w,*w,*Uvi,*w"))]
- "TARGET_REALLY_IWMMXT
- && ( register_operand (operands[0], DImode)
- || register_operand (operands[1], DImode))"
- "*
- switch (which_alternative)
- {
- case 0:
- case 1:
- case 2:
- return \"#\";
- case 3: case 4:
- return output_move_double (operands, true, NULL);
- case 5:
- return \"wmov%?\\t%0,%1\";
- case 6:
- return \"tmcrr%?\\t%0,%Q1,%R1\";
- case 7:
- return \"tmrrc%?\\t%Q0,%R0,%1\";
- case 8:
- return \"wldrd%?\\t%0,%1\";
- case 9:
- return \"wstrd%?\\t%1,%0\";
- case 10:
- return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
- case 11:
- return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
- case 12:
- if (TARGET_VFP_SINGLE)
- return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
- else
- return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
- case 13: case 14:
- return output_move_vfp (operands);
- default:
- gcc_unreachable ();
- }
- "
- [(set (attr "length") (cond [(eq_attr "alternative" "0,3,4") (const_int 8)
- (eq_attr "alternative" "1") (const_int 12)
- (eq_attr "alternative" "2") (const_int 16)
- (eq_attr "alternative" "12")
- (if_then_else
- (eq (symbol_ref "TARGET_VFP_SINGLE")
(const_int 1))
- (const_int 8)
- (const_int 4))]
- (const_int 4)))
- (set_attr "type" "*,*,*,load_8,store_8,*,*,*,*,*,f_mcrr,f_mrrc,\
- ffarithd,f_loadd,f_stored")
- (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*")
- (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")]
-)
-
-(define_insn "*iwmmxt_movsi_insn"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,
m,z,r,?z,?Uy,*t, r,*t,*t ,*Uv")
- (match_operand:SI 1 "general_operand" " rk,I,K,j,mi,rk,r,z,Uy, z,
r,*t,*t,*Uvi, *t"))]
- "TARGET_REALLY_IWMMXT
- && ( register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode))"
- "*
- switch (which_alternative)
- {
- case 0: return \"mov\\t%0, %1\";
- case 1: return \"mov\\t%0, %1\";
- case 2: return \"mvn\\t%0, #%B1\";
- case 3: return \"movw\\t%0, %1\";
- case 4: return \"ldr\\t%0, %1\";
- case 5: return \"str\\t%1, %0\";
- case 6: return \"tmcr\\t%0, %1\";
- case 7: return \"tmrc\\t%0, %1\";
- case 8: return arm_output_load_gr (operands);
- case 9: return \"wstrw\\t%1, %0\";
- case 10:return \"fmsr\\t%0, %1\";
- case 11:return \"fmrs\\t%0, %1\";
- case 12:return \"fcpys\\t%0, %1\\t%@ int\";
- case 13: case 14:
- return output_move_vfp (operands);
- default:
- gcc_unreachable ();
- }"
- [(set_attr "type" "*,*,*,*,load_4,store_4,*,*,*,*,f_mcr,f_mrc,\
- fmov,f_loads,f_stores")
- (set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*")
- (set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024,
*,*,*,*,1020,*")
- (set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *,
1012,*,*,*,1008,*")
- ;; Note - the "predicable" attribute is not allowed to have alternatives.
- ;; Since the wSTRw wCx instruction is not predicable, we cannot support
- ;; predicating any of the alternatives in this template. Instead,
- ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
- (set_attr "predicable" "no")
- ;; Also - we have to pretend that these insns clobber the condition code
- ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
- ;; them.
- (set_attr "conds" "clob")]
-)
-
-;; Because iwmmxt_movsi_insn is not predicable, we provide the
-;; cond_exec version explicitly, with appropriate constraints.
-
-(define_insn "*cond_iwmmxt_movsi_insn"
- [(cond_exec
- (match_operator 2 "arm_comparison_operator"
- [(match_operand 3 "cc_register" "")
- (const_int 0)])
- (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
- (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))]
- "TARGET_REALLY_IWMMXT
- && ( register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode))"
- "*
- switch (which_alternative)
- {
- case 0: return \"mov%?\\t%0, %1\";
- case 1: return \"mvn%?\\t%0, #%B1\";
- case 2: return \"ldr%?\\t%0, %1\";
- case 3: return \"str%?\\t%1, %0\";
- case 4: return \"tmcr%?\\t%0, %1\";
- default: return \"tmrc%?\\t%0, %1\";
- }"
- [(set_attr "type" "*,*,load_4,store_4,*,*")
- (set_attr "pool_range" "*,*,4096, *,*,*")
- (set_attr "neg_pool_range" "*,*,4084, *,*,*")]
-)
-
-(define_insn "mov<mode>_internal"
- [(set (match_operand:VMMX 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r,?m")
- (match_operand:VMMX 1 "general_operand" "y,y,mi,y,r,r,mi,r"))]
- "TARGET_REALLY_IWMMXT"
- "*
- switch (which_alternative)
- {
- case 0: return \"wmov%?\\t%0, %1\";
- case 1: return \"wstrd%?\\t%1, %0\";
- case 2: return \"wldrd%?\\t%0, %1\";
- case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
- case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
- case 5: return \"#\";
- default: return output_move_double (operands, true, NULL);
- }"
- [(set_attr "predicable" "yes")
- (set_attr "length" "4, 4, 4,4,4,8, 8,8")
- (set_attr "type"
"wmmx_wmov,wmmx_wstr,wmmx_wldr,wmmx_tmrrc,wmmx_tmcrr,*,load_4,store_4")
- (set_attr "pool_range" "*, *, 256,*,*,*, 256,*")
- (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244,*")]
-)
-
-(define_expand "iwmmxt_setwcgr0"
- [(set (reg:SI WCGR0)
- (match_operand:SI 0 "register_operand"))]
- "TARGET_REALLY_IWMMXT"
- {}
-)
-
-(define_expand "iwmmxt_setwcgr1"
- [(set (reg:SI WCGR1)
- (match_operand:SI 0 "register_operand"))]
- "TARGET_REALLY_IWMMXT"
- {}
-)
-
-(define_expand "iwmmxt_setwcgr2"
- [(set (reg:SI WCGR2)
- (match_operand:SI 0 "register_operand"))]
- "TARGET_REALLY_IWMMXT"
- {}
-)
-
-(define_expand "iwmmxt_setwcgr3"
- [(set (reg:SI WCGR3)
- (match_operand:SI 0 "register_operand"))]
- "TARGET_REALLY_IWMMXT"
- {}
-)
-
-(define_expand "iwmmxt_getwcgr0"
- [(set (match_operand:SI 0 "register_operand")
- (reg:SI WCGR0))]
- "TARGET_REALLY_IWMMXT"
- {}
-)
-
-(define_expand "iwmmxt_getwcgr1"
- [(set (match_operand:SI 0 "register_operand")
- (reg:SI WCGR1))]
- "TARGET_REALLY_IWMMXT"
- {}
-)
-
-(define_expand "iwmmxt_getwcgr2"
- [(set (match_operand:SI 0 "register_operand")
- (reg:SI WCGR2))]
- "TARGET_REALLY_IWMMXT"
- {}
-)
-
-(define_expand "iwmmxt_getwcgr3"
- [(set (match_operand:SI 0 "register_operand")
- (reg:SI WCGR3))]
- "TARGET_REALLY_IWMMXT"
- {}
-)
-
-(define_insn "*and<mode>3_iwmmxt"
- [(set (match_operand:VMMX 0 "register_operand" "=y")
- (and:VMMX (match_operand:VMMX 1 "register_operand" "y")
- (match_operand:VMMX 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wand\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wand")]
-)
-
-(define_insn "*ior<mode>3_iwmmxt"
- [(set (match_operand:VMMX 0 "register_operand" "=y")
- (ior:VMMX (match_operand:VMMX 1 "register_operand" "y")
- (match_operand:VMMX 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wor\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wor")]
-)
-
-(define_insn "*xor<mode>3_iwmmxt"
- [(set (match_operand:VMMX 0 "register_operand" "=y")
- (xor:VMMX (match_operand:VMMX 1 "register_operand" "y")
- (match_operand:VMMX 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wxor\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wxor")]
-)
-
-
-;; Vector add/subtract
-
-(define_insn "*add<mode>3_iwmmxt"
- [(set (match_operand:VMMX 0 "register_operand" "=y")
- (plus:VMMX (match_operand:VMMX 1 "register_operand" "y")
- (match_operand:VMMX 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wadd<MMX_char>%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wadd")]
-)
-
-(define_insn "ssaddv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
- (match_operand:V8QI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "waddbss%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wadd")]
-)
-
-(define_insn "ssaddv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
- (match_operand:V4HI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "waddhss%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wadd")]
-)
-
-(define_insn "ssaddv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
- (match_operand:V2SI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "waddwss%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wadd")]
-)
-
-(define_insn "usaddv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
- (match_operand:V8QI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "waddbus%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wadd")]
-)
-
-(define_insn "usaddv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
- (match_operand:V4HI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "waddhus%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wadd")]
-)
-
-(define_insn "usaddv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
- (match_operand:V2SI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "waddwus%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wadd")]
-)
-
-(define_insn "*sub<mode>3_iwmmxt"
- [(set (match_operand:VMMX 0 "register_operand" "=y")
- (minus:VMMX (match_operand:VMMX 1 "register_operand" "y")
- (match_operand:VMMX 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wsub<MMX_char>%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wsub")]
-)
-
-(define_insn "sssubv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
- (match_operand:V8QI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wsubbss%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wsub")]
-)
-
-(define_insn "sssubv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
- (match_operand:V4HI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wsubhss%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wsub")]
-)
-
-(define_insn "sssubv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
- (match_operand:V2SI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wsubwss%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wsub")]
-)
-
-(define_insn "ussubv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
- (match_operand:V8QI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wsubbus%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wsub")]
-)
-
-(define_insn "ussubv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
- (match_operand:V4HI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wsubhus%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wsub")]
-)
-
-(define_insn "ussubv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
- (match_operand:V2SI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wsubwus%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wsub")]
-)
-
-(define_insn "*mulv4hi3_iwmmxt"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
- (match_operand:V4HI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wmulul%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmul")]
-)
-
-(define_insn "smulv4hi3_highpart"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (truncate:V4HI
- (lshiftrt:V4SI
- (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1
"register_operand" "y"))
- (sign_extend:V4SI (match_operand:V4HI 2
"register_operand" "y")))
- (const_int 16))))]
- "TARGET_REALLY_IWMMXT"
- "wmulsm%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmul")]
-)
-
-(define_insn "umulv4hi3_highpart"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (truncate:V4HI
- (lshiftrt:V4SI
- (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1
"register_operand" "y"))
- (zero_extend:V4SI (match_operand:V4HI 2
"register_operand" "y")))
- (const_int 16))))]
- "TARGET_REALLY_IWMMXT"
- "wmulum%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmul")]
-)
-
-(define_insn "iwmmxt_wmacs"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI [(match_operand:DI 1 "register_operand" "0")
- (match_operand:V4HI 2 "register_operand" "y")
- (match_operand:V4HI 3 "register_operand" "y")]
UNSPEC_WMACS))]
- "TARGET_REALLY_IWMMXT"
- "wmacs%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmac")]
-)
-
-(define_insn "iwmmxt_wmacsz"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
- (match_operand:V4HI 2 "register_operand" "y")]
UNSPEC_WMACSZ))]
- "TARGET_REALLY_IWMMXT"
- "wmacsz%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmac")]
-)
-
-(define_insn "iwmmxt_wmacu"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI [(match_operand:DI 1 "register_operand" "0")
- (match_operand:V4HI 2 "register_operand" "y")
- (match_operand:V4HI 3 "register_operand" "y")]
UNSPEC_WMACU))]
- "TARGET_REALLY_IWMMXT"
- "wmacu%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmac")]
-)
-
-(define_insn "iwmmxt_wmacuz"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
- (match_operand:V4HI 2 "register_operand" "y")]
UNSPEC_WMACUZ))]
- "TARGET_REALLY_IWMMXT"
- "wmacuz%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmac")]
-)
-
-;; Same as xordi3, but don't show input operands so that we don't think
-;; they are live.
-(define_insn "iwmmxt_clrdi"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
- "TARGET_REALLY_IWMMXT"
- "wxor%?\\t%0, %0, %0"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wxor")]
-)
-
-;; Seems like cse likes to generate these, so we have to support them.
-
-(define_insn "iwmmxt_clrv8qi"
- [(set (match_operand:V8QI 0 "s_register_operand" "=y")
- (const_vector:V8QI [(const_int 0) (const_int 0)
- (const_int 0) (const_int 0)
- (const_int 0) (const_int 0)
- (const_int 0) (const_int 0)]))]
- "TARGET_REALLY_IWMMXT"
- "wxor%?\\t%0, %0, %0"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wxor")]
-)
-
-(define_insn "iwmmxt_clrv4hi"
- [(set (match_operand:V4HI 0 "s_register_operand" "=y")
- (const_vector:V4HI [(const_int 0) (const_int 0)
- (const_int 0) (const_int 0)]))]
- "TARGET_REALLY_IWMMXT"
- "wxor%?\\t%0, %0, %0"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wxor")]
-)
-
-(define_insn "iwmmxt_clrv2si"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (const_vector:V2SI [(const_int 0) (const_int 0)]))]
- "TARGET_REALLY_IWMMXT"
- "wxor%?\\t%0, %0, %0"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wxor")]
-)
-
-;; Unsigned averages/sum of absolute differences
-
-(define_insn "iwmmxt_uavgrndv8qi3"
- [(set (match_operand:V8QI 0
"register_operand" "=y")
- (truncate:V8QI
- (lshiftrt:V8HI
- (plus:V8HI
- (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1
"register_operand" "y"))
- (zero_extend:V8HI (match_operand:V8QI 2
"register_operand" "y")))
- (const_vector:V8HI [(const_int 1)
- (const_int 1)
- (const_int 1)
- (const_int 1)
- (const_int 1)
- (const_int 1)
- (const_int 1)
- (const_int 1)]))
- (const_int 1))))]
- "TARGET_REALLY_IWMMXT"
- "wavg2br%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wavg2")]
-)
-
-(define_insn "iwmmxt_uavgrndv4hi3"
- [(set (match_operand:V4HI 0
"register_operand" "=y")
- (truncate:V4HI
- (lshiftrt:V4SI
- (plus:V4SI
- (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1
"register_operand" "y"))
- (zero_extend:V4SI (match_operand:V4HI 2
"register_operand" "y")))
- (const_vector:V4SI [(const_int 1)
- (const_int 1)
- (const_int 1)
- (const_int 1)]))
- (const_int 1))))]
- "TARGET_REALLY_IWMMXT"
- "wavg2hr%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wavg2")]
-)
-
-(define_insn "iwmmxt_uavgv8qi3"
- [(set (match_operand:V8QI 0
"register_operand" "=y")
- (truncate:V8QI
- (lshiftrt:V8HI
- (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1
"register_operand" "y"))
- (zero_extend:V8HI (match_operand:V8QI 2
"register_operand" "y")))
- (const_int 1))))]
- "TARGET_REALLY_IWMMXT"
- "wavg2b%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wavg2")]
-)
-
-(define_insn "iwmmxt_uavgv4hi3"
- [(set (match_operand:V4HI 0
"register_operand" "=y")
- (truncate:V4HI
- (lshiftrt:V4SI
- (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1
"register_operand" "y"))
- (zero_extend:V4SI (match_operand:V4HI 2
"register_operand" "y")))
- (const_int 1))))]
- "TARGET_REALLY_IWMMXT"
- "wavg2h%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wavg2")]
-)
-
-;; Insert/extract/shuffle
-
-(define_insn "iwmmxt_tinsrb"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (vec_merge:V8QI
- (vec_duplicate:V8QI
- (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
- (match_operand:V8QI 1 "register_operand" "0")
- (match_operand:SI 3 "immediate_operand" "i")))]
- "TARGET_REALLY_IWMMXT"
- "*
- {
- return arm_output_iwmmxt_tinsr (operands);
- }
- "
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tinsr")]
-)
-
-(define_insn "iwmmxt_tinsrh"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_merge:V4HI
- (vec_duplicate:V4HI
- (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
- (match_operand:V4HI 1 "register_operand" "0")
- (match_operand:SI 3 "immediate_operand" "i")))]
- "TARGET_REALLY_IWMMXT"
- "*
- {
- return arm_output_iwmmxt_tinsr (operands);
- }
- "
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tinsr")]
-)
-
-(define_insn "iwmmxt_tinsrw"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_merge:V2SI
- (vec_duplicate:V2SI
- (match_operand:SI 2 "nonimmediate_operand" "r"))
- (match_operand:V2SI 1 "register_operand" "0")
- (match_operand:SI 3 "immediate_operand" "i")))]
- "TARGET_REALLY_IWMMXT"
- "*
- {
- return arm_output_iwmmxt_tinsr (operands);
- }
- "
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tinsr")]
-)
-
-(define_insn "iwmmxt_textrmub"
- [(set (match_operand:SI 0
"register_operand" "=r")
- (zero_extend:SI (vec_select:QI (match_operand:V8QI 1
"register_operand" "y")
- (parallel
- [(match_operand:SI 2
"immediate_operand" "i")]))))]
- "TARGET_REALLY_IWMMXT"
- "textrmub%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_textrm")]
-)
-
-(define_insn "iwmmxt_textrmsb"
- [(set (match_operand:SI 0
"register_operand" "=r")
- (sign_extend:SI (vec_select:QI (match_operand:V8QI 1
"register_operand" "y")
- (parallel
- [(match_operand:SI 2
"immediate_operand" "i")]))))]
- "TARGET_REALLY_IWMMXT"
- "textrmsb%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_textrm")]
-)
-
-(define_insn "iwmmxt_textrmuh"
- [(set (match_operand:SI 0
"register_operand" "=r")
- (zero_extend:SI (vec_select:HI (match_operand:V4HI 1
"register_operand" "y")
- (parallel
- [(match_operand:SI 2
"immediate_operand" "i")]))))]
- "TARGET_REALLY_IWMMXT"
- "textrmuh%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_textrm")]
-)
-
-(define_insn "iwmmxt_textrmsh"
- [(set (match_operand:SI 0
"register_operand" "=r")
- (sign_extend:SI (vec_select:HI (match_operand:V4HI 1
"register_operand" "y")
- (parallel
- [(match_operand:SI 2
"immediate_operand" "i")]))))]
- "TARGET_REALLY_IWMMXT"
- "textrmsh%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_textrm")]
-)
-
-;; There are signed/unsigned variants of this instruction, but they are
-;; pointless.
-(define_insn "iwmmxt_textrmw"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
- (parallel [(match_operand:SI 2 "immediate_operand"
"i")])))]
- "TARGET_REALLY_IWMMXT"
- "textrmsw%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_textrm")]
-)
-
-(define_insn "iwmmxt_wshufh"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
- (match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_WSHUFH))]
- "TARGET_REALLY_IWMMXT"
- "wshufh%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wshufh")]
-)
-
-;; Mask-generating comparisons
-;;
-;; Note - you cannot use patterns like these here:
-;;
-;; (set (match:<vector>) (<comparator>:<vector> (match:<vector>)
(match:<vector>)))
-;;
-;; Because GCC will assume that the truth value (1 or 0) is installed
-;; into the entire destination vector, (with the '1' going into the least
-;; significant element of the vector). This is not how these instructions
-;; behave.
-
-(define_insn "eqv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y")
- (match_operand:V8QI 2 "register_operand" "y")]
- VUNSPEC_WCMP_EQ))]
- "TARGET_REALLY_IWMMXT"
- "wcmpeqb%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wcmpeq")]
-)
-
-(define_insn "eqv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y")
- (match_operand:V4HI 2 "register_operand" "y")]
- VUNSPEC_WCMP_EQ))]
- "TARGET_REALLY_IWMMXT"
- "wcmpeqh%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wcmpeq")]
-)
-
-(define_insn "eqv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (unspec_volatile:V2SI
- [(match_operand:V2SI 1 "register_operand" "y")
- (match_operand:V2SI 2 "register_operand" "y")]
- VUNSPEC_WCMP_EQ))]
- "TARGET_REALLY_IWMMXT"
- "wcmpeqw%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wcmpeq")]
-)
-
-(define_insn "gtuv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y")
- (match_operand:V8QI 2 "register_operand" "y")]
- VUNSPEC_WCMP_GTU))]
- "TARGET_REALLY_IWMMXT"
- "wcmpgtub%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wcmpgt")]
-)
-
-(define_insn "gtuv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y")
- (match_operand:V4HI 2 "register_operand" "y")]
- VUNSPEC_WCMP_GTU))]
- "TARGET_REALLY_IWMMXT"
- "wcmpgtuh%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wcmpgt")]
-)
-
-(define_insn "gtuv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y")
- (match_operand:V2SI 2 "register_operand" "y")]
- VUNSPEC_WCMP_GTU))]
- "TARGET_REALLY_IWMMXT"
- "wcmpgtuw%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wcmpgt")]
-)
-
-(define_insn "gtv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y")
- (match_operand:V8QI 2 "register_operand" "y")]
- VUNSPEC_WCMP_GT))]
- "TARGET_REALLY_IWMMXT"
- "wcmpgtsb%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wcmpgt")]
-)
-
-(define_insn "gtv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y")
- (match_operand:V4HI 2 "register_operand" "y")]
- VUNSPEC_WCMP_GT))]
- "TARGET_REALLY_IWMMXT"
- "wcmpgtsh%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wcmpgt")]
-)
-
-(define_insn "gtv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y")
- (match_operand:V2SI 2 "register_operand" "y")]
- VUNSPEC_WCMP_GT))]
- "TARGET_REALLY_IWMMXT"
- "wcmpgtsw%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wcmpgt")]
-)
-
-;; Max/min insns
-
-(define_insn "*smax<mode>3_iwmmxt"
- [(set (match_operand:VMMX 0 "register_operand" "=y")
- (smax:VMMX (match_operand:VMMX 1 "register_operand" "y")
- (match_operand:VMMX 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wmaxs<MMX_char>%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmax")]
-)
-
-(define_insn "*umax<mode>3_iwmmxt"
- [(set (match_operand:VMMX 0 "register_operand" "=y")
- (umax:VMMX (match_operand:VMMX 1 "register_operand" "y")
- (match_operand:VMMX 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wmaxu<MMX_char>%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmax")]
-)
-
-(define_insn "*smin<mode>3_iwmmxt"
- [(set (match_operand:VMMX 0 "register_operand" "=y")
- (smin:VMMX (match_operand:VMMX 1 "register_operand" "y")
- (match_operand:VMMX 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wmins<MMX_char>%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmin")]
-)
-
-(define_insn "*umin<mode>3_iwmmxt"
- [(set (match_operand:VMMX 0 "register_operand" "=y")
- (umin:VMMX (match_operand:VMMX 1 "register_operand" "y")
- (match_operand:VMMX 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wminu<MMX_char>%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmin")]
-)
-
-;; Pack/unpack insns.
-
-(define_insn "iwmmxt_wpackhss"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (vec_concat:V8QI
- (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
- (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
- "TARGET_REALLY_IWMMXT"
- "wpackhss%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wpack")]
-)
-
-(define_insn "iwmmxt_wpackwss"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_concat:V4HI
- (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
- (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
- "TARGET_REALLY_IWMMXT"
- "wpackwss%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wpack")]
-)
-
-(define_insn "iwmmxt_wpackdss"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_concat:V2SI
- (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
- (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
- "TARGET_REALLY_IWMMXT"
- "wpackdss%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wpack")]
-)
-
-(define_insn "iwmmxt_wpackhus"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (vec_concat:V8QI
- (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
- (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
- "TARGET_REALLY_IWMMXT"
- "wpackhus%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wpack")]
-)
-
-(define_insn "iwmmxt_wpackwus"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_concat:V4HI
- (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
- (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
- "TARGET_REALLY_IWMMXT"
- "wpackwus%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wpack")]
-)
-
-(define_insn "iwmmxt_wpackdus"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_concat:V2SI
- (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
- (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
- "TARGET_REALLY_IWMMXT"
- "wpackdus%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wpack")]
-)
-
-(define_insn "iwmmxt_wunpckihb"
- [(set (match_operand:V8QI 0
"register_operand" "=y")
- (vec_merge:V8QI
- (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
- (parallel [(const_int 4)
- (const_int 0)
- (const_int 5)
- (const_int 1)
- (const_int 6)
- (const_int 2)
- (const_int 7)
- (const_int 3)]))
- (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
- (parallel [(const_int 0)
- (const_int 4)
- (const_int 1)
- (const_int 5)
- (const_int 2)
- (const_int 6)
- (const_int 3)
- (const_int 7)]))
- (const_int 85)))]
- "TARGET_REALLY_IWMMXT"
- "wunpckihb%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckih")]
-)
-
-(define_insn "iwmmxt_wunpckihh"
- [(set (match_operand:V4HI 0
"register_operand" "=y")
- (vec_merge:V4HI
- (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
- (parallel [(const_int 2)
- (const_int 0)
- (const_int 3)
- (const_int 1)]))
- (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 1)
- (const_int 3)]))
- (const_int 5)))]
- "TARGET_REALLY_IWMMXT"
- "wunpckihh%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckih")]
-)
-
-(define_insn "iwmmxt_wunpckihw"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_merge:V2SI
- (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
- (parallel [(const_int 1)
- (const_int 0)]))
- (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
- (parallel [(const_int 0)
- (const_int 1)]))
- (const_int 1)))]
- "TARGET_REALLY_IWMMXT"
- "wunpckihw%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckih")]
-)
-
-(define_insn "iwmmxt_wunpckilb"
- [(set (match_operand:V8QI 0
"register_operand" "=y")
- (vec_merge:V8QI
- (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
- (parallel [(const_int 0)
- (const_int 4)
- (const_int 1)
- (const_int 5)
- (const_int 2)
- (const_int 6)
- (const_int 3)
- (const_int 7)]))
- (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
- (parallel [(const_int 4)
- (const_int 0)
- (const_int 5)
- (const_int 1)
- (const_int 6)
- (const_int 2)
- (const_int 7)
- (const_int 3)]))
- (const_int 85)))]
- "TARGET_REALLY_IWMMXT"
- "wunpckilb%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckil")]
-)
-
-(define_insn "iwmmxt_wunpckilh"
- [(set (match_operand:V4HI 0
"register_operand" "=y")
- (vec_merge:V4HI
- (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 1)
- (const_int 3)]))
- (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
- (parallel [(const_int 2)
- (const_int 0)
- (const_int 3)
- (const_int 1)]))
- (const_int 5)))]
- "TARGET_REALLY_IWMMXT"
- "wunpckilh%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckil")]
-)
-
-(define_insn "iwmmxt_wunpckilw"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_merge:V2SI
- (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
- (parallel [(const_int 0)
- (const_int 1)]))
- (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
- (parallel [(const_int 1)
- (const_int 0)]))
- (const_int 1)))]
- "TARGET_REALLY_IWMMXT"
- "wunpckilw%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckil")]
-)
-
-(define_insn "iwmmxt_wunpckehub"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_select:V4HI
- (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
- (parallel [(const_int 4) (const_int 5)
- (const_int 6) (const_int 7)])))]
- "TARGET_REALLY_IWMMXT"
- "wunpckehub%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckeh")]
-)
-
-(define_insn "iwmmxt_wunpckehuh"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_select:V2SI
- (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
- (parallel [(const_int 2) (const_int 3)])))]
- "TARGET_REALLY_IWMMXT"
- "wunpckehuh%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckeh")]
-)
-
-(define_insn "iwmmxt_wunpckehuw"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (vec_select:DI
- (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
- (parallel [(const_int 1)])))]
- "TARGET_REALLY_IWMMXT"
- "wunpckehuw%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckeh")]
-)
-
-(define_insn "iwmmxt_wunpckehsb"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_select:V4HI
- (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
- (parallel [(const_int 4) (const_int 5)
- (const_int 6) (const_int 7)])))]
- "TARGET_REALLY_IWMMXT"
- "wunpckehsb%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckeh")]
-)
-
-(define_insn "iwmmxt_wunpckehsh"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_select:V2SI
- (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
- (parallel [(const_int 2) (const_int 3)])))]
- "TARGET_REALLY_IWMMXT"
- "wunpckehsh%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckeh")]
-)
-
-(define_insn "iwmmxt_wunpckehsw"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (vec_select:DI
- (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
- (parallel [(const_int 1)])))]
- "TARGET_REALLY_IWMMXT"
- "wunpckehsw%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckeh")]
-)
-
-(define_insn "iwmmxt_wunpckelub"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_select:V4HI
- (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
- (parallel [(const_int 0) (const_int 1)
- (const_int 2) (const_int 3)])))]
- "TARGET_REALLY_IWMMXT"
- "wunpckelub%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckel")]
-)
-
-(define_insn "iwmmxt_wunpckeluh"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_select:V2SI
- (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
- (parallel [(const_int 0) (const_int 1)])))]
- "TARGET_REALLY_IWMMXT"
- "wunpckeluh%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckel")]
-)
-
-(define_insn "iwmmxt_wunpckeluw"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (vec_select:DI
- (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
- (parallel [(const_int 0)])))]
- "TARGET_REALLY_IWMMXT"
- "wunpckeluw%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckel")]
-)
-
-(define_insn "iwmmxt_wunpckelsb"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_select:V4HI
- (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
- (parallel [(const_int 0) (const_int 1)
- (const_int 2) (const_int 3)])))]
- "TARGET_REALLY_IWMMXT"
- "wunpckelsb%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckel")]
-)
-
-(define_insn "iwmmxt_wunpckelsh"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_select:V2SI
- (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
- (parallel [(const_int 0) (const_int 1)])))]
- "TARGET_REALLY_IWMMXT"
- "wunpckelsh%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckel")]
-)
-
-(define_insn "iwmmxt_wunpckelsw"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (vec_select:DI
- (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
- (parallel [(const_int 0)])))]
- "TARGET_REALLY_IWMMXT"
- "wunpckelsw%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wunpckel")]
-)
-
-;; Shifts
-
-(define_insn "ror<mode>3"
- [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
- (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
- (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
- "TARGET_REALLY_IWMMXT"
- "*
- switch (which_alternative)
- {
- case 0:
- return \"wror<MMX_char>g%?\\t%0, %1, %2\";
- case 1:
- return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands,
true);
- default:
- gcc_unreachable ();
- }
- "
- [(set_attr "predicable" "yes")
- (set_attr "arch" "*, iwmmxt2")
- (set_attr "type" "wmmx_wror, wmmx_wror")]
-)
-
-(define_insn "ashr<mode>3_iwmmxt"
- [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
- (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
- (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
- "TARGET_REALLY_IWMMXT"
- "*
- switch (which_alternative)
- {
- case 0:
- return \"wsra<MMX_char>g%?\\t%0, %1, %2\";
- case 1:
- return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands,
true);
- default:
- gcc_unreachable ();
- }
- "
- [(set_attr "predicable" "yes")
- (set_attr "arch" "*, iwmmxt2")
- (set_attr "type" "wmmx_wsra, wmmx_wsra")]
-)
-
-(define_insn "lshr<mode>3_iwmmxt"
- [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
- (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
- (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
- "TARGET_REALLY_IWMMXT"
- "*
- switch (which_alternative)
- {
- case 0:
- return \"wsrl<MMX_char>g%?\\t%0, %1, %2\";
- case 1:
- return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands,
false);
- default:
- gcc_unreachable ();
- }
- "
- [(set_attr "predicable" "yes")
- (set_attr "arch" "*, iwmmxt2")
- (set_attr "type" "wmmx_wsrl, wmmx_wsrl")]
-)
-
-(define_insn "ashl<mode>3_iwmmxt"
- [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
- (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
- (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
- "TARGET_REALLY_IWMMXT"
- "*
- switch (which_alternative)
- {
- case 0:
- return \"wsll<MMX_char>g%?\\t%0, %1, %2\";
- case 1:
- return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands,
false);
- default:
- gcc_unreachable ();
- }
- "
- [(set_attr "predicable" "yes")
- (set_attr "arch" "*, iwmmxt2")
- (set_attr "type" "wmmx_wsll, wmmx_wsll")]
-)
-
-(define_insn "ror<mode>3_di"
- [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
- (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
- (match_operand:DI 2 "imm_or_reg_operand" "y,i")))]
- "TARGET_REALLY_IWMMXT"
- "*
- switch (which_alternative)
- {
- case 0:
- return \"wror<MMX_char>%?\\t%0, %1, %2\";
- case 1:
- return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands,
true);
- default:
- gcc_unreachable ();
- }
- "
- [(set_attr "predicable" "yes")
- (set_attr "arch" "*, iwmmxt2")
- (set_attr "type" "wmmx_wror, wmmx_wror")]
-)
-
-(define_insn "ashr<mode>3_di"
- [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
- (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
- (match_operand:DI 2 "imm_or_reg_operand" "y,i")))]
- "TARGET_REALLY_IWMMXT"
- "*
- switch (which_alternative)
- {
- case 0:
- return \"wsra<MMX_char>%?\\t%0, %1, %2\";
- case 1:
- return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands,
true);
- default:
- gcc_unreachable ();
- }
- "
- [(set_attr "predicable" "yes")
- (set_attr "arch" "*, iwmmxt2")
- (set_attr "type" "wmmx_wsra, wmmx_wsra")]
-)
-
-(define_insn "lshr<mode>3_di"
- [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
- (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
- (match_operand:DI 2 "register_operand" "y,i")))]
- "TARGET_REALLY_IWMMXT"
- "*
- switch (which_alternative)
- {
- case 0:
- return \"wsrl<MMX_char>%?\\t%0, %1, %2\";
- case 1:
- return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands,
false);
- default:
- gcc_unreachable ();
- }
- "
- [(set_attr "predicable" "yes")
- (set_attr "arch" "*, iwmmxt2")
- (set_attr "type" "wmmx_wsrl, wmmx_wsrl")]
-)
-
-(define_insn "ashl<mode>3_di"
- [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
- (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
- (match_operand:DI 2 "imm_or_reg_operand" "y,i")))]
- "TARGET_REALLY_IWMMXT"
- "*
- switch (which_alternative)
- {
- case 0:
- return \"wsll<MMX_char>%?\\t%0, %1, %2\";
- case 1:
- return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands,
false);
- default:
- gcc_unreachable ();
- }
- "
- [(set_attr "predicable" "yes")
- (set_attr "arch" "*, iwmmxt2")
- (set_attr "type" "wmmx_wsll, wmmx_wsll")]
-)
-
-(define_insn "iwmmxt_wmadds"
- [(set (match_operand:V2SI 0
"register_operand" "=y")
- (plus:V2SI
- (mult:V2SI
- (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1
"register_operand" "y"))
- (parallel [(const_int 1) (const_int 3)]))
- (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2
"register_operand" "y"))
- (parallel [(const_int 1) (const_int 3)])))
- (mult:V2SI
- (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
- (parallel [(const_int 0) (const_int 2)]))
- (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
- (parallel [(const_int 0) (const_int 2)])))))]
- "TARGET_REALLY_IWMMXT"
- "wmadds%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmadd")]
-)
-
-(define_insn "iwmmxt_wmaddu"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (plus:V2SI
- (mult:V2SI
- (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1
"register_operand" "y"))
- (parallel [(const_int 1) (const_int 3)]))
- (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2
"register_operand" "y"))
- (parallel [(const_int 1) (const_int 3)])))
- (mult:V2SI
- (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
- (parallel [(const_int 0) (const_int 2)]))
- (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
- (parallel [(const_int 0) (const_int 2)])))))]
- "TARGET_REALLY_IWMMXT"
- "wmaddu%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmadd")]
-)
-
-(define_insn "iwmmxt_tmia"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (plus:DI (match_operand:DI 1 "register_operand" "0")
- (mult:DI (sign_extend:DI
- (match_operand:SI 2 "register_operand" "r"))
- (sign_extend:DI
- (match_operand:SI 3 "register_operand" "r")))))]
- "TARGET_REALLY_IWMMXT"
- "tmia%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tmia")]
-)
-
-(define_insn "iwmmxt_tmiaph"
- [(set (match_operand:DI 0
"register_operand" "=y")
- (plus:DI (match_operand:DI 1
"register_operand" "0")
- (plus:DI
- (mult:DI (sign_extend:DI
- (truncate:HI (match_operand:SI 2
"register_operand" "r")))
- (sign_extend:DI
- (truncate:HI (match_operand:SI 3
"register_operand" "r"))))
- (mult:DI (sign_extend:DI
- (truncate:HI (ashiftrt:SI (match_dup 2)
(const_int 16))))
- (sign_extend:DI
- (truncate:HI (ashiftrt:SI (match_dup 3)
(const_int 16))))))))]
- "TARGET_REALLY_IWMMXT"
- "tmiaph%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tmiaph")]
-)
-
-(define_insn "iwmmxt_tmiabb"
- [(set (match_operand:DI 0
"register_operand" "=y")
- (plus:DI (match_operand:DI 1 "register_operand"
"0")
- (mult:DI (sign_extend:DI
- (truncate:HI (match_operand:SI 2 "register_operand"
"r")))
- (sign_extend:DI
- (truncate:HI (match_operand:SI 3 "register_operand"
"r"))))))]
- "TARGET_REALLY_IWMMXT"
- "tmiabb%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tmiaxy")]
-)
-
-(define_insn "iwmmxt_tmiatb"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (plus:DI (match_operand:DI 1 "register_operand" "0")
- (mult:DI (sign_extend:DI
- (truncate:HI
- (ashiftrt:SI
- (match_operand:SI 2 "register_operand" "r")
- (const_int 16))))
- (sign_extend:DI
- (truncate:HI
- (match_operand:SI 3 "register_operand"
"r"))))))]
- "TARGET_REALLY_IWMMXT"
- "tmiatb%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tmiaxy")]
-)
-
-(define_insn "iwmmxt_tmiabt"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (plus:DI (match_operand:DI 1 "register_operand" "0")
- (mult:DI (sign_extend:DI
- (truncate:HI
- (match_operand:SI 2 "register_operand" "r")))
- (sign_extend:DI
- (truncate:HI
- (ashiftrt:SI
- (match_operand:SI 3 "register_operand" "r")
- (const_int 16)))))))]
- "TARGET_REALLY_IWMMXT"
- "tmiabt%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tmiaxy")]
-)
-
-(define_insn "iwmmxt_tmiatt"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (plus:DI (match_operand:DI 1 "register_operand" "0")
- (mult:DI (sign_extend:DI
- (truncate:HI
- (ashiftrt:SI
- (match_operand:SI 2 "register_operand" "r")
- (const_int 16))))
- (sign_extend:DI
- (truncate:HI
- (ashiftrt:SI
- (match_operand:SI 3 "register_operand" "r")
- (const_int 16)))))))]
- "TARGET_REALLY_IWMMXT"
- "tmiatt%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tmiaxy")]
-)
-
-(define_insn "iwmmxt_tmovmskb"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
UNSPEC_TMOVMSK))]
- "TARGET_REALLY_IWMMXT"
- "tmovmskb%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tmovmsk")]
-)
-
-(define_insn "iwmmxt_tmovmskh"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")]
UNSPEC_TMOVMSK))]
- "TARGET_REALLY_IWMMXT"
- "tmovmskh%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tmovmsk")]
-)
-
-(define_insn "iwmmxt_tmovmskw"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")]
UNSPEC_TMOVMSK))]
- "TARGET_REALLY_IWMMXT"
- "tmovmskw%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tmovmsk")]
-)
-
-(define_insn "iwmmxt_waccb"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")]
UNSPEC_WACC))]
- "TARGET_REALLY_IWMMXT"
- "waccb%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wacc")]
-)
-
-(define_insn "iwmmxt_wacch"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")]
UNSPEC_WACC))]
- "TARGET_REALLY_IWMMXT"
- "wacch%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wacc")]
-)
-
-(define_insn "iwmmxt_waccw"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")]
UNSPEC_WACC))]
- "TARGET_REALLY_IWMMXT"
- "waccw%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wacc")]
-)
-
-;; use unspec here to prevent 8 * imm to be optimized by cse
-(define_insn "iwmmxt_waligni"
- [(set (match_operand:V8QI 0
"register_operand" "=y")
- (unspec:V8QI [(subreg:V8QI
- (ashiftrt:TI
- (subreg:TI (vec_concat:V16QI
- (match_operand:V8QI 1 "register_operand"
"y")
- (match_operand:V8QI 2 "register_operand"
"y")) 0)
- (mult:SI
- (match_operand:SI 3
"immediate_operand" "i")
- (const_int 8))) 0)] UNSPEC_WALIGNI))]
- "TARGET_REALLY_IWMMXT"
- "waligni%?\\t%0, %1, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_waligni")]
-)
-
-(define_insn "iwmmxt_walignr"
- [(set (match_operand:V8QI 0 "register_operand"
"=y")
- (subreg:V8QI (ashiftrt:TI
- (subreg:TI (vec_concat:V16QI
- (match_operand:V8QI 1 "register_operand"
"y")
- (match_operand:V8QI 2 "register_operand"
"y")) 0)
- (mult:SI
- (zero_extract:SI (match_operand:SI 3
"register_operand" "z") (const_int 3) (const_int 0))
- (const_int 8))) 0))]
- "TARGET_REALLY_IWMMXT"
- "walignr%U3%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_walignr")]
-)
-
-(define_insn "iwmmxt_walignr0"
- [(set (match_operand:V8QI 0 "register_operand"
"=y")
- (subreg:V8QI (ashiftrt:TI
- (subreg:TI (vec_concat:V16QI
- (match_operand:V8QI 1 "register_operand"
"y")
- (match_operand:V8QI 2 "register_operand"
"y")) 0)
- (mult:SI
- (zero_extract:SI (reg:SI WCGR0) (const_int 3)
(const_int 0))
- (const_int 8))) 0))]
- "TARGET_REALLY_IWMMXT"
- "walignr0%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_walignr")]
-)
-
-(define_insn "iwmmxt_walignr1"
- [(set (match_operand:V8QI 0 "register_operand"
"=y")
- (subreg:V8QI (ashiftrt:TI
- (subreg:TI (vec_concat:V16QI
- (match_operand:V8QI 1 "register_operand"
"y")
- (match_operand:V8QI 2 "register_operand"
"y")) 0)
- (mult:SI
- (zero_extract:SI (reg:SI WCGR1) (const_int 3)
(const_int 0))
- (const_int 8))) 0))]
- "TARGET_REALLY_IWMMXT"
- "walignr1%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_walignr")]
-)
-
-(define_insn "iwmmxt_walignr2"
- [(set (match_operand:V8QI 0 "register_operand"
"=y")
- (subreg:V8QI (ashiftrt:TI
- (subreg:TI (vec_concat:V16QI
- (match_operand:V8QI 1 "register_operand"
"y")
- (match_operand:V8QI 2 "register_operand"
"y")) 0)
- (mult:SI
- (zero_extract:SI (reg:SI WCGR2) (const_int 3)
(const_int 0))
- (const_int 8))) 0))]
- "TARGET_REALLY_IWMMXT"
- "walignr2%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_walignr")]
-)
-
-(define_insn "iwmmxt_walignr3"
- [(set (match_operand:V8QI 0 "register_operand"
"=y")
- (subreg:V8QI (ashiftrt:TI
- (subreg:TI (vec_concat:V16QI
- (match_operand:V8QI 1 "register_operand"
"y")
- (match_operand:V8QI 2 "register_operand"
"y")) 0)
- (mult:SI
- (zero_extract:SI (reg:SI WCGR3) (const_int 3)
(const_int 0))
- (const_int 8))) 0))]
- "TARGET_REALLY_IWMMXT"
- "walignr3%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_walignr")]
-)
-
-(define_insn "iwmmxt_wsadb"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (unspec:V2SI [
- (match_operand:V2SI 1 "register_operand" "0")
- (match_operand:V8QI 2 "register_operand" "y")
- (match_operand:V8QI 3 "register_operand" "y")]
UNSPEC_WSAD))]
- "TARGET_REALLY_IWMMXT"
- "wsadb%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wsad")]
-)
-
-(define_insn "iwmmxt_wsadh"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (unspec:V2SI [
- (match_operand:V2SI 1 "register_operand" "0")
- (match_operand:V4HI 2 "register_operand" "y")
- (match_operand:V4HI 3 "register_operand" "y")]
UNSPEC_WSAD))]
- "TARGET_REALLY_IWMMXT"
- "wsadh%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wsad")]
-)
-
-(define_insn "iwmmxt_wsadbz"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (unspec:V2SI [(match_operand:V8QI 1 "register_operand" "y")
- (match_operand:V8QI 2 "register_operand" "y")]
UNSPEC_WSADZ))]
- "TARGET_REALLY_IWMMXT"
- "wsadbz%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wsad")]
-)
-
-(define_insn "iwmmxt_wsadhz"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (unspec:V2SI [(match_operand:V4HI 1 "register_operand" "y")
- (match_operand:V4HI 2 "register_operand" "y")]
UNSPEC_WSADZ))]
- "TARGET_REALLY_IWMMXT"
- "wsadhz%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wsad")]
-)
-
-(include "iwmmxt2.md")
diff --git a/gcc/config/arm/iwmmxt2.md b/gcc/config/arm/iwmmxt2.md
deleted file mode 100644
index 74cd1484dfd..00000000000
--- a/gcc/config/arm/iwmmxt2.md
+++ /dev/null
@@ -1,903 +0,0 @@
-;; Patterns for the Intel Wireless MMX technology architecture.
-;; Copyright (C) 2011-2025 Free Software Foundation, Inc.
-;; Written by Marvell, Inc.
-;;
-;; This file is part of GCC.
-;;
-;; GCC is free software; you can redistribute it and/or modify it
-;; under the terms of the GNU General Public License as published
-;; by the Free Software Foundation; either version 3, or (at your
-;; option) any later version.
-
-;; GCC is distributed in the hope that it will be useful, but WITHOUT
-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
-;; License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING3. If not see
-;; <http://www.gnu.org/licenses/>.
-
-(define_insn "iwmmxt_wabs<mode>3"
- [(set (match_operand:VMMX 0 "register_operand" "=y")
- (unspec:VMMX [(match_operand:VMMX 1 "register_operand" "y")]
UNSPEC_WABS))]
- "TARGET_REALLY_IWMMXT"
- "wabs<MMX_char>%?\\t%0, %1"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wabs")]
-)
-
-(define_insn "iwmmxt_wabsdiffb"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (truncate:V8QI
- (abs:V8HI
- (minus:V8HI
- (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
- (zero_extend:V8HI (match_operand:V8QI 2 "register_operand"
"y"))))))]
- "TARGET_REALLY_IWMMXT"
- "wabsdiffb%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wabsdiff")]
-)
-
-(define_insn "iwmmxt_wabsdiffh"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (truncate: V4HI
- (abs:V4SI
- (minus:V4SI
- (zero_extend:V4SI (match_operand:V4HI 1 "register_operand"
"y"))
- (zero_extend:V4SI (match_operand:V4HI 2 "register_operand"
"y"))))))]
- "TARGET_REALLY_IWMMXT"
- "wabsdiffh%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wabsdiff")]
-)
-
-(define_insn "iwmmxt_wabsdiffw"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (truncate: V2SI
- (abs:V2DI
- (minus:V2DI
- (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
- (zero_extend:V2DI (match_operand:V2SI 2 "register_operand"
"y"))))))]
- "TARGET_REALLY_IWMMXT"
- "wabsdiffw%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wabsdiff")]
-)
-
-(define_insn "iwmmxt_waddsubhx"
- [(set (match_operand:V4HI 0
"register_operand" "=y")
- (vec_merge:V4HI
- (ss_minus:V4HI
- (match_operand:V4HI 1
"register_operand" "y")
- (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
- (parallel [(const_int 1) (const_int 0) (const_int
3) (const_int 2)])))
- (ss_plus:V4HI
- (match_dup 1)
- (vec_select:V4HI (match_dup 2)
- (parallel [(const_int 1) (const_int 0) (const_int
3) (const_int 2)])))
- (const_int 10)))]
- "TARGET_REALLY_IWMMXT"
- "waddsubhx%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_waddsubhx")]
-)
-
-(define_insn "iwmmxt_wsubaddhx"
- [(set (match_operand:V4HI 0
"register_operand" "=y")
- (vec_merge:V4HI
- (ss_plus:V4HI
- (match_operand:V4HI 1
"register_operand" "y")
- (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
- (parallel [(const_int 1) (const_int 0) (const_int
3) (const_int 2)])))
- (ss_minus:V4HI
- (match_dup 1)
- (vec_select:V4HI (match_dup 2)
- (parallel [(const_int 1) (const_int 0) (const_int
3) (const_int 2)])))
- (const_int 10)))]
- "TARGET_REALLY_IWMMXT"
- "wsubaddhx%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wsubaddhx")]
-)
-
-(define_insn "addc<mode>3"
- [(set (match_operand:VMMX2 0 "register_operand" "=y")
- (unspec:VMMX2
- [(plus:VMMX2
- (match_operand:VMMX2 1 "register_operand" "y")
- (match_operand:VMMX2 2 "register_operand" "y"))] UNSPEC_WADDC))]
- "TARGET_REALLY_IWMMXT"
- "wadd<MMX_char>c%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wadd")]
-)
-
-(define_insn "iwmmxt_avg4"
-[(set (match_operand:V8QI 0 "register_operand"
"=y")
- (truncate:V8QI
- (vec_select:V8HI
- (vec_merge:V8HI
- (lshiftrt:V8HI
- (plus:V8HI
- (plus:V8HI
- (plus:V8HI
- (plus:V8HI
- (zero_extend:V8HI (match_operand:V8QI 1
"register_operand" "y"))
- (zero_extend:V8HI (match_operand:V8QI 2
"register_operand" "y")))
- (vec_select:V8HI (zero_extend:V8HI (match_dup 1))
- (parallel [(const_int 7) (const_int 0)
(const_int 1) (const_int 2)
- (const_int 3) (const_int 4)
(const_int 5) (const_int 6)])))
- (vec_select:V8HI (zero_extend:V8HI (match_dup 2))
- (parallel [(const_int 7) (const_int 0)
(const_int 1) (const_int 2)
- (const_int 3) (const_int 4)
(const_int 5) (const_int 6)])))
- (const_vector:V8HI [(const_int 1) (const_int 1) (const_int 1)
(const_int 1)
- (const_int 1) (const_int 1) (const_int 1)
(const_int 1)]))
- (const_int 2))
- (const_vector:V8HI [(const_int 0) (const_int 0) (const_int 0)
(const_int 0)
- (const_int 0) (const_int 0) (const_int 0)
(const_int 0)])
- (const_int 254))
- (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 4)
- (const_int 5) (const_int 6) (const_int 7) (const_int
0)]))))]
- "TARGET_REALLY_IWMMXT"
- "wavg4%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wavg4")]
-)
-
-(define_insn "iwmmxt_avg4r"
- [(set (match_operand:V8QI 0
"register_operand" "=y")
- (truncate:V8QI
- (vec_select:V8HI
- (vec_merge:V8HI
- (lshiftrt:V8HI
- (plus:V8HI
- (plus:V8HI
- (plus:V8HI
- (plus:V8HI
- (zero_extend:V8HI (match_operand:V8QI 1
"register_operand" "y"))
- (zero_extend:V8HI (match_operand:V8QI 2
"register_operand" "y")))
- (vec_select:V8HI (zero_extend:V8HI (match_dup 1))
- (parallel [(const_int 7) (const_int 0)
(const_int 1) (const_int 2)
- (const_int 3) (const_int 4)
(const_int 5) (const_int 6)])))
- (vec_select:V8HI (zero_extend:V8HI (match_dup 2))
- (parallel [(const_int 7) (const_int 0)
(const_int 1) (const_int 2)
- (const_int 3) (const_int 4)
(const_int 5) (const_int 6)])))
- (const_vector:V8HI [(const_int 2) (const_int 2) (const_int 2)
(const_int 2)
- (const_int 2) (const_int 2) (const_int 2)
(const_int 2)]))
- (const_int 2))
- (const_vector:V8HI [(const_int 0) (const_int 0) (const_int 0)
(const_int 0)
- (const_int 0) (const_int 0) (const_int 0)
(const_int 0)])
- (const_int 254))
- (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 4)
- (const_int 5) (const_int 6) (const_int 7) (const_int
0)]))))]
- "TARGET_REALLY_IWMMXT"
- "wavg4r%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wavg4")]
-)
-
-(define_insn "iwmmxt_wmaddsx"
- [(set (match_operand:V2SI 0
"register_operand" "=y")
- (plus:V2SI
- (mult:V2SI
- (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1
"register_operand" "y"))
- (parallel [(const_int 1) (const_int 3)]))
- (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2
"register_operand" "y"))
- (parallel [(const_int 0) (const_int 2)])))
- (mult:V2SI
- (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
- (parallel [(const_int 0) (const_int 2)]))
- (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
- (parallel [(const_int 1) (const_int 3)])))))]
- "TARGET_REALLY_IWMMXT"
- "wmaddsx%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmadd")]
-)
-
-(define_insn "iwmmxt_wmaddux"
- [(set (match_operand:V2SI 0
"register_operand" "=y")
- (plus:V2SI
- (mult:V2SI
- (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1
"register_operand" "y"))
- (parallel [(const_int 1) (const_int 3)]))
- (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2
"register_operand" "y"))
- (parallel [(const_int 0) (const_int 2)])))
- (mult:V2SI
- (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
- (parallel [(const_int 0) (const_int 2)]))
- (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
- (parallel [(const_int 1) (const_int 3)])))))]
- "TARGET_REALLY_IWMMXT"
- "wmaddux%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmadd")]
-)
-
-(define_insn "iwmmxt_wmaddsn"
- [(set (match_operand:V2SI 0
"register_operand" "=y")
- (minus:V2SI
- (mult:V2SI
- (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1
"register_operand" "y"))
- (parallel [(const_int 0) (const_int 2)]))
- (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2
"register_operand" "y"))
- (parallel [(const_int 0) (const_int 2)])))
- (mult:V2SI
- (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
- (parallel [(const_int 1) (const_int 3)]))
- (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
- (parallel [(const_int 1) (const_int 3)])))))]
- "TARGET_REALLY_IWMMXT"
- "wmaddsn%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmadd")]
-)
-
-(define_insn "iwmmxt_wmaddun"
- [(set (match_operand:V2SI 0
"register_operand" "=y")
- (minus:V2SI
- (mult:V2SI
- (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1
"register_operand" "y"))
- (parallel [(const_int 0) (const_int 2)]))
- (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2
"register_operand" "y"))
- (parallel [(const_int 0) (const_int 2)])))
- (mult:V2SI
- (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
- (parallel [(const_int 1) (const_int 3)]))
- (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
- (parallel [(const_int 1) (const_int 3)])))))]
- "TARGET_REALLY_IWMMXT"
- "wmaddun%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmadd")]
-)
-
-(define_insn "iwmmxt_wmulwsm"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (truncate:V2SI
- (ashiftrt:V2DI
- (mult:V2DI
- (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
- (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
- (const_int 32))))]
- "TARGET_REALLY_IWMMXT"
- "wmulwsm%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmulw")]
-)
-
-(define_insn "iwmmxt_wmulwum"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (truncate:V2SI
- (lshiftrt:V2DI
- (mult:V2DI
- (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
- (zero_extend:V2DI (match_operand:V2SI 2 "register_operand" "y")))
- (const_int 32))))]
- "TARGET_REALLY_IWMMXT"
- "wmulwum%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmulw")]
-)
-
-(define_insn "iwmmxt_wmulsmr"
- [(set (match_operand:V4HI 0 "register_operand"
"=y")
- (truncate:V4HI
- (ashiftrt:V4SI
- (plus:V4SI
- (mult:V4SI
- (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
- (sign_extend:V4SI (match_operand:V4HI 2 "register_operand"
"y")))
- (const_vector:V4SI [(const_int 32768)
- (const_int 32768)
- (const_int 32768)]))
- (const_int 16))))]
- "TARGET_REALLY_IWMMXT"
- "wmulsmr%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmul")]
-)
-
-(define_insn "iwmmxt_wmulumr"
- [(set (match_operand:V4HI 0 "register_operand"
"=y")
- (truncate:V4HI
- (lshiftrt:V4SI
- (plus:V4SI
- (mult:V4SI
- (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
- (zero_extend:V4SI (match_operand:V4HI 2 "register_operand"
"y")))
- (const_vector:V4SI [(const_int 32768)
- (const_int 32768)
- (const_int 32768)
- (const_int 32768)]))
- (const_int 16))))]
- "TARGET_REALLY_IWMMXT"
- "wmulumr%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmul")]
-)
-
-(define_insn "iwmmxt_wmulwsmr"
- [(set (match_operand:V2SI 0 "register_operand"
"=y")
- (truncate:V2SI
- (ashiftrt:V2DI
- (plus:V2DI
- (mult:V2DI
- (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
- (sign_extend:V2DI (match_operand:V2SI 2 "register_operand"
"y")))
- (const_vector:V2DI [(const_int 2147483648)
- (const_int 2147483648)]))
- (const_int 32))))]
- "TARGET_REALLY_IWMMXT"
- "wmulwsmr%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmul")]
-)
-
-(define_insn "iwmmxt_wmulwumr"
- [(set (match_operand:V2SI 0 "register_operand"
"=y")
- (truncate:V2SI
- (lshiftrt:V2DI
- (plus:V2DI
- (mult:V2DI
- (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
- (zero_extend:V2DI (match_operand:V2SI 2 "register_operand"
"y")))
- (const_vector:V2DI [(const_int 2147483648)
- (const_int 2147483648)]))
- (const_int 32))))]
- "TARGET_REALLY_IWMMXT"
- "wmulwumr%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmulw")]
-)
-
-(define_insn "iwmmxt_wmulwl"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (mult:V2SI
- (match_operand:V2SI 1 "register_operand" "y")
- (match_operand:V2SI 2 "register_operand" "y")))]
- "TARGET_REALLY_IWMMXT"
- "wmulwl%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmulw")]
-)
-
-(define_insn "iwmmxt_wqmulm"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
- (match_operand:V4HI 2 "register_operand" "y")]
UNSPEC_WQMULM))]
- "TARGET_REALLY_IWMMXT"
- "wqmulm%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wqmulm")]
-)
-
-(define_insn "iwmmxt_wqmulwm"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "y")
- (match_operand:V2SI 2 "register_operand" "y")]
UNSPEC_WQMULWM))]
- "TARGET_REALLY_IWMMXT"
- "wqmulwm%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wqmulwm")]
-)
-
-(define_insn "iwmmxt_wqmulmr"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
- (match_operand:V4HI 2 "register_operand" "y")]
UNSPEC_WQMULMR))]
- "TARGET_REALLY_IWMMXT"
- "wqmulmr%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wqmulm")]
-)
-
-(define_insn "iwmmxt_wqmulwmr"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "y")
- (match_operand:V2SI 2 "register_operand" "y")]
UNSPEC_WQMULWMR))]
- "TARGET_REALLY_IWMMXT"
- "wqmulwmr%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wqmulwm")]
-)
-
-(define_insn "iwmmxt_waddbhusm"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (vec_concat:V8QI
- (const_vector:V4QI [(const_int 0) (const_int 0) (const_int 0)
(const_int 0)])
- (us_truncate:V4QI
- (ss_plus:V4HI
- (match_operand:V4HI 1 "register_operand" "y")
- (zero_extend:V4HI
- (vec_select:V4QI (match_operand:V8QI 2 "register_operand" "y")
- (parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))))))]
- "TARGET_REALLY_IWMMXT"
- "waddbhusm%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_waddbhus")]
-)
-
-(define_insn "iwmmxt_waddbhusl"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (vec_concat:V8QI
- (us_truncate:V4QI
- (ss_plus:V4HI
- (match_operand:V4HI 1 "register_operand" "y")
- (zero_extend:V4HI
- (vec_select:V4QI (match_operand:V8QI 2 "register_operand" "y")
- (parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))))
- (const_vector:V4QI [(const_int 0) (const_int 0) (const_int 0)
(const_int 0)])))]
- "TARGET_REALLY_IWMMXT"
- "waddbhusl%?\\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_waddbhus")]
-)
-
-(define_insn "iwmmxt_wqmiabb"
- [(set (match_operand:V2SI 0
"register_operand" "=y")
- (unspec:V2SI [(match_operand:V2SI 1
"register_operand" "0")
- (zero_extract:V4HI (match_operand:V4HI 2
"register_operand" "y") (const_int 16) (const_int 0))
- (zero_extract:V4HI (match_dup 2) (const_int 16)
(const_int 32))
- (zero_extract:V4HI (match_operand:V4HI 3
"register_operand" "y") (const_int 16) (const_int 0))
- (zero_extract:V4HI (match_dup 3) (const_int 16)
(const_int 32))] UNSPEC_WQMIAxy))]
- "TARGET_REALLY_IWMMXT"
- "wqmiabb%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wqmiaxy")]
-)
-
-(define_insn "iwmmxt_wqmiabt"
- [(set (match_operand:V2SI 0
"register_operand" "=y")
- (unspec:V2SI [(match_operand:V2SI 1
"register_operand" "0")
- (zero_extract:V4HI (match_operand:V4HI 2
"register_operand" "y") (const_int 16) (const_int 0))
- (zero_extract:V4HI (match_dup 2) (const_int 16)
(const_int 32))
- (zero_extract:V4HI (match_operand:V4HI 3
"register_operand" "y") (const_int 16) (const_int 16))
- (zero_extract:V4HI (match_dup 3) (const_int 16)
(const_int 48))] UNSPEC_WQMIAxy))]
- "TARGET_REALLY_IWMMXT"
- "wqmiabt%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wqmiaxy")]
-)
-
-(define_insn "iwmmxt_wqmiatb"
- [(set (match_operand:V2SI 0
"register_operand" "=y")
- (unspec:V2SI [(match_operand:V2SI 1
"register_operand" "0")
- (zero_extract:V4HI (match_operand:V4HI 2
"register_operand" "y") (const_int 16) (const_int 16))
- (zero_extract:V4HI (match_dup 2) (const_int 16)
(const_int 48))
- (zero_extract:V4HI (match_operand:V4HI 3
"register_operand" "y") (const_int 16) (const_int 0))
- (zero_extract:V4HI (match_dup 3) (const_int 16)
(const_int 32))] UNSPEC_WQMIAxy))]
- "TARGET_REALLY_IWMMXT"
- "wqmiatb%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wqmiaxy")]
-)
-
-(define_insn "iwmmxt_wqmiatt"
- [(set (match_operand:V2SI 0
"register_operand" "=y")
- (unspec:V2SI [(match_operand:V2SI 1
"register_operand" "0")
- (zero_extract:V4HI (match_operand:V4HI 2
"register_operand" "y") (const_int 16) (const_int 16))
- (zero_extract:V4HI (match_dup 2) (const_int 16)
(const_int 48))
- (zero_extract:V4HI (match_operand:V4HI 3
"register_operand" "y") (const_int 16) (const_int 16))
- (zero_extract:V4HI (match_dup 3) (const_int 16)
(const_int 48))] UNSPEC_WQMIAxy))]
- "TARGET_REALLY_IWMMXT"
- "wqmiatt%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wqmiaxy")]
-)
-
-(define_insn "iwmmxt_wqmiabbn"
- [(set (match_operand:V2SI 0
"register_operand" "=y")
- (unspec:V2SI [(match_operand:V2SI 1
"register_operand" "0")
- (zero_extract:V4HI (match_operand:V4HI 2
"register_operand" "y") (const_int 16) (const_int 0))
- (zero_extract:V4HI (match_dup 2) (const_int 16)
(const_int 32))
- (zero_extract:V4HI (match_operand:V4HI 3
"register_operand" "y") (const_int 16) (const_int 0))
- (zero_extract:V4HI (match_dup 3) (const_int 16)
(const_int 32))] UNSPEC_WQMIAxyn))]
- "TARGET_REALLY_IWMMXT"
- "wqmiabbn%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wqmiaxy")]
-)
-
-(define_insn "iwmmxt_wqmiabtn"
- [(set (match_operand:V2SI 0
"register_operand" "=y")
- (unspec:V2SI [(match_operand:V2SI 1
"register_operand" "0")
- (zero_extract:V4HI (match_operand:V4HI 2
"register_operand" "y") (const_int 16) (const_int 0))
- (zero_extract:V4HI (match_dup 2) (const_int 16)
(const_int 32))
- (zero_extract:V4HI (match_operand:V4HI 3
"register_operand" "y") (const_int 16) (const_int 16))
- (zero_extract:V4HI (match_dup 3) (const_int 16)
(const_int 48))] UNSPEC_WQMIAxyn))]
- "TARGET_REALLY_IWMMXT"
- "wqmiabtn%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wqmiaxy")]
-)
-
-(define_insn "iwmmxt_wqmiatbn"
- [(set (match_operand:V2SI 0
"register_operand" "=y")
- (unspec:V2SI [(match_operand:V2SI 1
"register_operand" "0")
- (zero_extract:V4HI (match_operand:V4HI 2
"register_operand" "y") (const_int 16) (const_int 16))
- (zero_extract:V4HI (match_dup 2) (const_int 16)
(const_int 48))
- (zero_extract:V4HI (match_operand:V4HI 3
"register_operand" "y") (const_int 16) (const_int 0))
- (zero_extract:V4HI (match_dup 3) (const_int 16)
(const_int 32))] UNSPEC_WQMIAxyn))]
- "TARGET_REALLY_IWMMXT"
- "wqmiatbn%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wqmiaxy")]
-)
-
-(define_insn "iwmmxt_wqmiattn"
- [(set (match_operand:V2SI 0
"register_operand" "=y")
- (unspec:V2SI [(match_operand:V2SI 1
"register_operand" "0")
- (zero_extract:V4HI (match_operand:V4HI 2
"register_operand" "y") (const_int 16) (const_int 16))
- (zero_extract:V4HI (match_dup 2) (const_int 16) (const_int
48))
- (zero_extract:V4HI (match_operand:V4HI 3
"register_operand" "y") (const_int 16) (const_int 16))
- (zero_extract:V4HI (match_dup 3) (const_int 16) (const_int
48))] UNSPEC_WQMIAxyn))]
- "TARGET_REALLY_IWMMXT"
- "wqmiattn%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wqmiaxy")]
-)
-
-(define_insn "iwmmxt_wmiabb"
- [(set (match_operand:DI 0
"register_operand" "=y")
- (plus:DI (match_operand:DI 1 "register_operand"
"0")
- (plus:DI
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 2 "register_operand"
"y")
- (parallel [(const_int 0)])))
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 3 "register_operand"
"y")
- (parallel [(const_int 0)]))))
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_dup 2)
- (parallel [(const_int 2)])))
- (sign_extend:DI
- (vec_select:HI (match_dup 3)
- (parallel [(const_int 2)])))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiabb%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiaxy")]
-)
-
-(define_insn "iwmmxt_wmiabt"
- [(set (match_operand:DI 0
"register_operand" "=y")
- (plus:DI (match_operand:DI 1 "register_operand"
"0")
- (plus:DI
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 2 "register_operand"
"y")
- (parallel [(const_int 0)])))
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 3 "register_operand"
"y")
- (parallel [(const_int 1)]))))
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_dup 2)
- (parallel [(const_int 2)])))
- (sign_extend:DI
- (vec_select:HI (match_dup 3)
- (parallel [(const_int 3)])))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiabt%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiaxy")]
-)
-
-(define_insn "iwmmxt_wmiatb"
- [(set (match_operand:DI 0
"register_operand" "=y")
- (plus:DI (match_operand:DI 1 "register_operand"
"0")
- (plus:DI
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 2 "register_operand"
"y")
- (parallel [(const_int 1)])))
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 3 "register_operand"
"y")
- (parallel [(const_int 0)]))))
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_dup 2)
- (parallel [(const_int 3)])))
- (sign_extend:DI
- (vec_select:HI (match_dup 3)
- (parallel [(const_int 2)])))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiatb%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiaxy")]
-)
-
-(define_insn "iwmmxt_wmiatt"
- [(set (match_operand:DI 0 "register_operand"
"=y")
- (plus:DI (match_operand:DI 1 "register_operand" "0")
- (plus:DI
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 2 "register_operand" "y")
- (parallel [(const_int 1)])))
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 3 "register_operand" "y")
- (parallel [(const_int 1)]))))
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_dup 2)
- (parallel [(const_int 3)])))
- (sign_extend:DI
- (vec_select:HI (match_dup 3)
- (parallel [(const_int 3)])))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiatt%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiaxy")]
-)
-
-(define_insn "iwmmxt_wmiabbn"
- [(set (match_operand:DI 0
"register_operand" "=y")
- (minus:DI (match_operand:DI 1 "register_operand"
"0")
- (plus:DI
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 2 "register_operand"
"y")
- (parallel [(const_int 0)])))
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 3 "register_operand"
"y")
- (parallel [(const_int 0)]))))
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_dup 2)
- (parallel [(const_int 2)])))
- (sign_extend:DI
- (vec_select:HI (match_dup 3)
- (parallel [(const_int 2)])))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiabbn%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiaxy")]
-)
-
-(define_insn "iwmmxt_wmiabtn"
- [(set (match_operand:DI 0
"register_operand" "=y")
- (minus:DI (match_operand:DI 1 "register_operand"
"0")
- (plus:DI
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 2 "register_operand"
"y")
- (parallel [(const_int 0)])))
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 3 "register_operand"
"y")
- (parallel [(const_int 1)]))))
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_dup 2)
- (parallel [(const_int 2)])))
- (sign_extend:DI
- (vec_select:HI (match_dup 3)
- (parallel [(const_int 3)])))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiabtn%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiaxy")]
-)
-
-(define_insn "iwmmxt_wmiatbn"
- [(set (match_operand:DI 0 "register_operand"
"=y")
- (minus:DI (match_operand:DI 1 "register_operand"
"0")
- (plus:DI
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 2 "register_operand"
"y")
- (parallel [(const_int 1)])))
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 3 "register_operand"
"y")
- (parallel [(const_int 0)]))))
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_dup 2)
- (parallel [(const_int 3)])))
- (sign_extend:DI
- (vec_select:HI (match_dup 3)
- (parallel [(const_int 2)])))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiatbn%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiaxy")]
-)
-
-(define_insn "iwmmxt_wmiattn"
- [(set (match_operand:DI 0 "register_operand"
"=y")
- (minus:DI (match_operand:DI 1 "register_operand"
"0")
- (plus:DI
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 2 "register_operand"
"y")
- (parallel [(const_int 1)])))
- (sign_extend:DI
- (vec_select:HI (match_operand:V4HI 3 "register_operand"
"y")
- (parallel [(const_int 1)]))))
- (mult:DI
- (sign_extend:DI
- (vec_select:HI (match_dup 2)
- (parallel [(const_int 3)])))
- (sign_extend:DI
- (vec_select:HI (match_dup 3)
- (parallel [(const_int 3)])))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiattn%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiaxy")]
-)
-
-(define_insn "iwmmxt_wmiawbb"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (plus:DI
- (match_operand:DI 1 "register_operand" "0")
- (mult:DI
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 2
"register_operand" "y") (parallel [(const_int 0)])))
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 3
"register_operand" "y") (parallel [(const_int 0)]))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiawbb%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiawxy")]
-)
-
-(define_insn "iwmmxt_wmiawbt"
- [(set (match_operand:DI 0
"register_operand" "=y")
- (plus:DI
- (match_operand:DI 1
"register_operand" "0")
- (mult:DI
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 2
"register_operand" "y") (parallel [(const_int 0)])))
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 3
"register_operand" "y") (parallel [(const_int 1)]))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiawbt%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiawxy")]
-)
-
-(define_insn "iwmmxt_wmiawtb"
- [(set (match_operand:DI 0
"register_operand" "=y")
- (plus:DI
- (match_operand:DI 1
"register_operand" "0")
- (mult:DI
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 2
"register_operand" "y") (parallel [(const_int 1)])))
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 3
"register_operand" "y") (parallel [(const_int 0)]))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiawtb%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiawxy")]
-)
-
-(define_insn "iwmmxt_wmiawtt"
-[(set (match_operand:DI 0
"register_operand" "=y")
- (plus:DI
- (match_operand:DI 1
"register_operand" "0")
- (mult:DI
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 2
"register_operand" "y") (parallel [(const_int 1)])))
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 3
"register_operand" "y") (parallel [(const_int 1)]))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiawtt%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiawxy")]
-)
-
-(define_insn "iwmmxt_wmiawbbn"
- [(set (match_operand:DI 0
"register_operand" "=y")
- (minus:DI
- (match_operand:DI 1
"register_operand" "0")
- (mult:DI
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 2
"register_operand" "y") (parallel [(const_int 0)])))
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 3
"register_operand" "y") (parallel [(const_int 0)]))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiawbbn%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiawxy")]
-)
-
-(define_insn "iwmmxt_wmiawbtn"
- [(set (match_operand:DI 0
"register_operand" "=y")
- (minus:DI
- (match_operand:DI 1
"register_operand" "0")
- (mult:DI
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 2
"register_operand" "y") (parallel [(const_int 0)])))
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 3
"register_operand" "y") (parallel [(const_int 1)]))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiawbtn%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiawxy")]
-)
-
-(define_insn "iwmmxt_wmiawtbn"
- [(set (match_operand:DI 0
"register_operand" "=y")
- (minus:DI
- (match_operand:DI 1
"register_operand" "0")
- (mult:DI
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 2
"register_operand" "y") (parallel [(const_int 1)])))
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 3
"register_operand" "y") (parallel [(const_int 0)]))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiawtbn%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiawxy")]
-)
-
-(define_insn "iwmmxt_wmiawttn"
- [(set (match_operand:DI 0
"register_operand" "=y")
- (minus:DI
- (match_operand:DI 1
"register_operand" "0")
- (mult:DI
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 2
"register_operand" "y") (parallel [(const_int 1)])))
- (sign_extend:DI (vec_select:SI (match_operand:V2SI 3
"register_operand" "y") (parallel [(const_int 1)]))))))]
- "TARGET_REALLY_IWMMXT"
- "wmiawttn%?\\t%0, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmiawxy")]
-)
-
-(define_insn "iwmmxt_wmerge"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (ior:DI
- (ashift:DI
- (match_operand:DI 2 "register_operand" "y")
- (minus:SI
- (const_int 64)
- (mult:SI
- (match_operand:SI 3 "immediate_operand" "i")
- (const_int 8))))
- (lshiftrt:DI
- (ashift:DI
- (match_operand:DI 1 "register_operand" "y")
- (mult:SI
- (match_dup 3)
- (const_int 8)))
- (mult:SI
- (match_dup 3)
- (const_int 8)))))]
- "TARGET_REALLY_IWMMXT"
- "wmerge%?\\t%0, %1, %2, %3"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_wmerge")]
-)
-
-(define_insn "iwmmxt_tandc<mode>3"
- [(set (reg:CC CC_REGNUM)
- (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TANDC) 0))
- (unspec:CC [(reg:SI 15)] UNSPEC_TANDC)]
- "TARGET_REALLY_IWMMXT"
- "tandc<MMX_char>%?\\t r15"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_tandc")]
-)
-
-(define_insn "iwmmxt_torc<mode>3"
- [(set (reg:CC CC_REGNUM)
- (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TORC) 0))
- (unspec:CC [(reg:SI 15)] UNSPEC_TORC)]
- "TARGET_REALLY_IWMMXT"
- "torc<MMX_char>%?\\t r15"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_torc")]
-)
-
-(define_insn "iwmmxt_torvsc<mode>3"
- [(set (reg:CC CC_REGNUM)
- (subreg:CC (unspec:VMMX [(const_int 0)] UNSPEC_TORVSC) 0))
- (unspec:CC [(reg:SI 15)] UNSPEC_TORVSC)]
- "TARGET_REALLY_IWMMXT"
- "torvsc<MMX_char>%?\\t r15"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_torvsc")]
-)
-
-(define_insn "iwmmxt_textrc<mode>3"
- [(set (reg:CC CC_REGNUM)
- (subreg:CC (unspec:VMMX [(const_int 0)
- (match_operand:SI 0 "immediate_operand" "i")]
UNSPEC_TEXTRC) 0))
- (unspec:CC [(reg:SI 15)] UNSPEC_TEXTRC)]
- "TARGET_REALLY_IWMMXT"
- "textrc<MMX_char>%?\\t r15, %0"
- [(set_attr "predicable" "yes")
- (set_attr "type" "wmmx_textrc")]
-)
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 75c06d9be25..57d4ec66088 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -806,14 +806,8 @@ (define_predicate "thumb_cbrch_target_operand"
;;-------------------------------------------------------------------------
;;
-;; iWMMXt predicates
-;;
-
-(define_predicate "imm_or_reg_operand"
- (ior (match_operand 0 "immediate_operand")
- (match_operand 0 "register_operand")))
-
;; Neon predicates
+;;
(define_predicate "const_multiple_of_8_operand"
(match_code "const_int")
diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm
index 641f8f538a6..83ed6dd4531 100644
--- a/gcc/config/arm/t-arm
+++ b/gcc/config/arm/t-arm
@@ -50,8 +50,6 @@ MD_INCLUDES= $(srcdir)/config/arm/arm1020e.md \
$(srcdir)/config/arm/fa726te.md \
$(srcdir)/config/arm/fmp626.md \
$(srcdir)/config/arm/iterators.md \
- $(srcdir)/config/arm/iwmmxt.md \
- $(srcdir)/config/arm/iwmmxt2.md \
$(srcdir)/config/arm/ldmstm.md \
$(srcdir)/config/arm/ldrdstrd.md \
$(srcdir)/config/arm/marvell-f-iwmmxt.md \
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index a03609d1de4..c1ee97248e0 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -21,7 +21,6 @@
;; UNSPEC Usage:
;; Note: sin and cos are no-longer used.
;; Unspec enumerators for Neon are defined in neon.md.
-;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md
(define_c_enum "unspec" [
UNSPEC_PUSH_MULT ; `push multiple' operation:
@@ -42,17 +41,6 @@ (define_c_enum "unspec" [
; and stack frame generation. Operand 0 is the
; register to "use".
UNSPEC_CHECK_ARCH ; Set CCs to indicate 26-bit or 32-bit mode.
- UNSPEC_WSHUFH ; Used by the intrinsic form of the iWMMXt WSHUFH
instruction.
- UNSPEC_WACC ; Used by the intrinsic form of the iWMMXt WACC
instruction.
- UNSPEC_TMOVMSK ; Used by the intrinsic form of the iWMMXt TMOVMSK
instruction.
- UNSPEC_WSAD ; Used by the intrinsic form of the iWMMXt WSAD
instruction.
- UNSPEC_WSADZ ; Used by the intrinsic form of the iWMMXt WSADZ
instruction.
- UNSPEC_WMACS ; Used by the intrinsic form of the iWMMXt WMACS
instruction.
- UNSPEC_WMACU ; Used by the intrinsic form of the iWMMXt WMACU
instruction.
- UNSPEC_WMACSZ ; Used by the intrinsic form of the iWMMXt WMACSZ
instruction.
- UNSPEC_WMACUZ ; Used by the intrinsic form of the iWMMXt WMACUZ
instruction.
- UNSPEC_CLRDI ; Used by the intrinsic form of the iWMMXt CLRDI
instruction.
- UNSPEC_WALIGNI ; Used by the intrinsic form of the iWMMXt WALIGN
instruction.
UNSPEC_TLS ; A symbol that has been treated properly for TLS
usage.
UNSPEC_PIC_LABEL ; A label used for PIC access that does not appear in
the
; instruction stream.
@@ -164,18 +152,6 @@ (define_c_enum "unspec" [
(define_c_enum "unspec" [
- UNSPEC_WADDC ; Used by the intrinsic form of the iWMMXt WADDC
instruction.
- UNSPEC_WABS ; Used by the intrinsic form of the iWMMXt WABS
instruction.
- UNSPEC_WQMULWMR ; Used by the intrinsic form of the iWMMXt WQMULWMR
instruction.
- UNSPEC_WQMULMR ; Used by the intrinsic form of the iWMMXt WQMULMR
instruction.
- UNSPEC_WQMULWM ; Used by the intrinsic form of the iWMMXt WQMULWM
instruction.
- UNSPEC_WQMULM ; Used by the intrinsic form of the iWMMXt
WQMULM instruction.
- UNSPEC_WQMIAxyn ; Used by the intrinsic form of the iWMMXt WMIAxyn
instruction.
- UNSPEC_WQMIAxy ; Used by the intrinsic form of the iWMMXt WMIAxy
instruction.
- UNSPEC_TANDC ; Used by the intrinsic form of the iWMMXt TANDC
instruction.
- UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC
instruction.
- UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt
TORVSC instruction.
- UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt
TEXTRC instruction.
UNSPEC_GET_FPSCR_NZCVQC ; Represent fetch of FPSCR_nzcvqc content.
])
@@ -205,12 +181,7 @@ (define_c_enum "unspecv" [
; a 64-bit object.
VUNSPEC_POOL_16 ; `pool-entry(16)'. An entry in the constant pool for
; a 128-bit object.
- VUNSPEC_TMRC ; Used by the iWMMXt TMRC instruction.
- VUNSPEC_TMCR ; Used by the iWMMXt TMCR instruction.
VUNSPEC_ALIGN8 ; 8-byte alignment version of VUNSPEC_ALIGN
- VUNSPEC_WCMP_EQ ; Used by the iWMMXt WCMPEQ instructions
- VUNSPEC_WCMP_GTU ; Used by the iWMMXt WCMPGTU instructions
- VUNSPEC_WCMP_GT ; Used by the iwMMXT WCMPGT instructions
VUNSPEC_EH_RETURN ; Use to override the return address for exception
; handling.
VUNSPEC_ATOMIC_CAS ; Represent an atomic compare swap.
--
2.43.0
