Like all other targets, we add RISC-V into vect_cmdline_needed. This patch fixes following FAILs:
FAIL: gcc.dg/tree-ssa/gen-vect-11b.c scan-tree-dump-times vect "vectorized 0 loops" 1 FAIL: gcc.dg/tree-ssa/gen-vect-11c.c scan-tree-dump-times vect "vectorized 0 loops" 1 FAIL: gcc.dg/tree-ssa/gen-vect-26.c scan-tree-dump-times vect "Alignment of access forced using peeling" 1 FAIL: gcc.dg/tree-ssa/gen-vect-28.c scan-tree-dump-times vect "Alignment of access forced using peeling" 1 gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add RISC-V. --- gcc/testsuite/lib/target-supports.exp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 17a87db0007..285817ef16e 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4036,7 +4036,8 @@ proc check_effective_target_vect_cmdline_needed { } { || ([istarget sparc*-*-*] && [check_effective_target_sparc_vis]) || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) || [istarget aarch64*-*-*] - || [istarget amdgcn*-*-*]} { + || [istarget amdgcn*-*-*] + || [istarget riscv*-*-*]} { return 0 } else { return 1 -- 2.36.3