Hi! On Mon, Mar 28, 2022 at 12:27:05PM -0400, Michael Meissner wrote: > In looking at PR target/99293, I noticed that the code in the insn > vsx_splat_<mode>_reg used "vecmove" as the "type" insn attribute when the > "mtvsrdd" is generated. It should use "mfvsr". I also added a "p9v" isa > attribute for that alternative.
s/mfvsr/mtvsr/ But, mtvsrd and mtvsrdd have very different scheduling properties (like, on p10 it is 1 cycle vs. 3 cycles). Also, there are two insn patterns for mtvsrdd, and you are only touching one here. > * config/rs6000/rs6000.md (vsx_splat_<mode>_reg): Use the correct > insn type attribute. Add "p9v" isa attribute for generating the > mtvsrdd instruction. This is in vsx.md, instead. > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -4580,7 +4580,8 @@ (define_insn "vsx_splat_<mode>_reg" > "@ > xxpermdi %x0,%x1,%x1,0 > mtvsrdd %x0,%1,%1" > - [(set_attr "type" "vecperm,vecmove")]) > + [(set_attr "type" "vecperm,mtvsr") > + (set_attr "isa" "*,p9v")]) "we" requires "p9v". Please do a full conversion when getting rid of this? That includes requiring TARGET_POWERPC64 for it (not -m64 as its documentation says; the existing implementation of "we" is correct). Segher
