Hi!
On Fri, Dec 20, 2019 at 06:38:32PM -0500, Michael Meissner wrote:
> --- gcc/config/rs6000/rs6000.c (revision 279553)
> +++ gcc/config/rs6000/rs6000.c (working copy)
> @@ -6792,9 +6792,17 @@ rs6000_adjust_vec_address (rtx scalar_re
> HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
> rtx offset_rtx = GEN_INT (offset);
>
> - if (IN_RANGE (offset, -32768, 32767)
> + /* 16-bit offset. */
> + if (SIGNED_INTEGER_16BIT_P (offset)
> && (scalar_size < 8 || (offset & 0x3) == 0))
> new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
We probably should have a macro for this, hrm. The
reg_or_aligned_short_operand predicate is the closest we have right now.
> + /* 34-bit offset if we have prefixed addresses. */
> + else if (TARGET_PREFIXED_ADDR && SIGNED_INTEGER_34BIT_P (offset))
> + new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
This is cint34_operand.
And maybe we want both in one, for convenience?
(Something for the future of course, not this patch).
> + /* Offset overflowed, move offset to the temporary (which will likely
> + be split), and do X-FORM addressing. */
> else
> {
The comment should go here, instead (after the {).
> + /* Make sure we don't overwrite the temporary if the element being
> + extracted is variable, and we've put the offset into base_tmp
> + previously. */
> + else if (rtx_equal_p (base_tmp, element_offset))
> + emit_insn (gen_add2_insn (base_tmp, op1));
Register equality (in the same mode, as we have here) is just "==". Is
that what we need here, or should it be reg_mentioned_p?
This whole function is too complex (and it writes TARGET_POWERPC64 where
it needs TARGET_64BIT, for example).
The patch is okay for trunk (with the comment moved, and the rtx_equal_p
fixed). Thanks!
Segher
