In addition to the previous patch to aid in transitioning the PowerPC long
double format to IEEE 128-bit, I have some additional patches that are needed.
The previous patch is:
https://gcc.gnu.org/ml/gcc-patches/2018-06/msg00634.html
This patch fixes the power8 implementation of copysign for IEEE 128-bit
floating point. In particular, the way the temporary register was allocated
did not use the normal GCC conventions of using a clobber with match_scratch.
Because the constraint did not include a '&', the temporary register could have
used one of the input registers.
Note, the GLIBC library that I used is not fully converted. I'm ignoring the
issues that are due to the library, and just focusing on the compiler support.
I have done separate bootstraps on a little endian power8 system with the long
double type set to IBM extended and IEEE 128-bit extended. There were no
regressions in using this patch. Can I check it in, and eventually back port
it to GCC 8.2 with the other long double transition patches.
2018-06-13 Michael Meissner <[email protected]>
* config/rs6000/rs6000.md (copysign<mode>3, IEEE iterator): Rework
copysign of float128 on ISA 2.07 to use an explicit clobber,
instead of passing in a temporary.
(copysign<mode>3_soft): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: [email protected], phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 261512)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -14102,11 +14102,8 @@ (define_expand "copysign<mode>3"
emit_insn (gen_copysign<mode>3_hard (operands[0], operands[1],
operands[2]));
else
- {
- rtx tmp = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_copysign<mode>3_soft (operands[0], operands[1],
- operands[2], tmp));
- }
+ emit_insn (gen_copysign<mode>3_soft (operands[0], operands[1],
+ operands[2]));
DONE;
})
@@ -14125,9 +14122,9 @@ (define_insn "copysign<mode>3_soft"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
[(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")
- (match_operand:IEEE128 3 "altivec_register_operand" "+v")]
- UNSPEC_COPYSIGN))]
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")]
+ UNSPEC_COPYSIGN))
+ (clobber (match_scratch:IEEE128 3 "=&v"))]
"!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1"
[(set_attr "type" "veccomplex")
